ETS B

35 papers

YearTitle / Authors
2007"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
200712th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007
2007A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter.
Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro
2007A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus.
Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson
2007A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.
Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek
2007Adaptive Debug and Diagnosis without Fault Dictionaries.
Stefan Holst, Hans-Joachim Wunderlich
2007An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.
Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
2007Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.
Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware
2007Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
2007Communication-Centric SoC Debug Using Transactions.
Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
2007Computation and Application of Absolute Dominators in Industrial Designs.
Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel
2007DERRIC: A Tool for Unified Logic Diagnosis.
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007Diagnostic Test Generation Based on Subsets of Faults.
Irith Pomeranz, Sudhakar M. Reddy
2007Digital Generation of Signals for Low Cost RF BIST.
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
2007Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007Electronics Design-for-Test: Past, Present and Future.
Ben Bennetts
2007Embedded Tutorial on Low Power Test.
Nicola Nicolici, Xiaoqing Wen
2007Embedded Tutorial: IC Test Cost Benchmarking.
Klaus Luther
2007FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests.
Ivo Koren, Frank Demmerle, Roland May, Martin Kaibel, Sebastian Sattler
2007If It's All about Yield, Why Talk about Testing?
Rene Segers
2007On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2007Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.
Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara
2007Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2007PPM Reduction on Embedded Memories in System on Chip.
Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero
2007Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.
Tao Xu, Krishnendu Chakrabarty
2007Purely Digital BIST for Any PLL or DLL.
Stephen K. Sunter, Aubin Roy
2007Selecting Power-Optimal SBST Routines for On-Line Processor Testing.
Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos
2007Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.
Luca Sterpone, Massimo Violante
2007System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies.
Carlos Arthur Lang Lisbôa, Marcelo Ienczczak Erigson, Luigi Carro
2007System-in-Package, a Combination of Challenges and Solutions.
Philippe Cauvet, Serge Bernard, Michel Renovell
2007Test Configurations for Diagnosing Faulty Links in NoC Switches.
Jaan Raik, Raimund Ubar, Vineeth Govind
2007Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2007Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives.
Shaji Krishnan, Rene Jonker, Leon van de Logt
2007Wafer Level Reliability Screens.
Peter C. Maxwell