ETS B

40 papers

YearTitle / Authors
2006"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
200611th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006
2006A 22n March Test for Realistic Static Linked Faults in SRAMs.
Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006A DFT Architecture for Asynchronous Networks-on-Chip.
Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach
2006A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare.
Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun
2006A Low Cost Alternative Method for Harmonics Estimation in a BIST Context.
Vincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy
2006A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications.
Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret
2006A Transparent based Programmable Memory BIST.
Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa
2006A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2006Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.
Kentaroh Katoh, Hideo Ito
2006Convolutional Compactors with Variable Polynomials.
Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2006Deterministic Logic BIST for Transition Fault Testing.
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
2006Dynamic Voltage Scaling Aware Delay Fault Testing.
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod
2006Enhancing Delay Fault Coverage through Low Power Segmented Scan.
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2006Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits.
Erik Schüler, Daniel Scain Farenzena, Luigi Carro
2006Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators.
Gildas Léger, Adoración Rueda
2006FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
2006Fault Collapsing for Transition Faults Using Extended Transition Faults.
Irith Pomeranz, Sudhakar M. Reddy
2006Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2006Fault Injection-based Reliability Evaluation of SoPCs.
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
2006Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study.
Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
2006Innovation and Wealth Creation from Technology.
Robin Saxby
2006Living with Failure: Lessons from Nature?
Steve B. Furber
2006Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.
Gefu Xu, Adit D. Singh
2006Low Cost Parametric Failure Diagnosis of RF Transceivers.
Donghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee
2006Low-Cost Online Testing of Asynchronous Handshakes.
Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov
2006Minimal March Tests for Dynamic Faults in Random Access Memories.
Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2006New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).
Bill Eklow, Ben Bennetts
2006On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.
Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz
2006On-Chip Test Generation Using Linear Subspaces.
Ramashis Das, Igor L. Markov, John P. Hayes
2006On-Chip Time Measurement Architecture with Femtosecond Timing Resolution.
Matthew Collins, Bashir M. Al-Hashimi
2006Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters.
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
2006Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test.
Shalabh Goyal, Abhijit Chatterjee, Mike Atia
2006Retention-Aware Test Scheduling for BISTed Embedded SRAMs.
Qiang Xu, Baosheng Wang, F. Y. Young
2006Single-Event Upset Analysis and Protection in High Speed Circuits.
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
2006Soft-Error Rate Testing of Deep-Submicron Integrated Circuits.
Tino Heijmen, André Nieuwland
2006Test-per-Clock Detection, Localization and Identification of Interconnect Faults.
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2006Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.
Yu-Jen Huang, Jin-Fu Li
2006Testing and Diagnosis of Power Switches in SOCs.
Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2006Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes