DSD C

80 papers

YearTitle / Authors
202427th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, August 28-30, 2024
20243D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project.
Himar Fabelo, Raquel León, Emanuele Torti, Santiago Marco, Max Verbers, Yann Falevoz, Yolanda Ramallo-Fariña, Christian Weis, Ana M. Wägner, Eduardo Juárez Martínez, Claudio Rial, Alfonso Lagares, Gustav Burström, Francesco Leporati, Elisa Marenzi, Teresa Cervero, Miquel Moretó, Giovanni Danese, Sveta Zinger, Francesca Manni, Maria Luisa Alvarez-Male, Jesús Morera, Bernardino Clavo, Gustavo M. Callicó, Stratum Consortium
20246G-TakeOff: Holistic 3D Networks for 6G Wireless Communications.
Marko S. Andjelkovic, Nebojsa Maletic, Nicola Miglioranza, Milos Krstic, Enrico Koeck, Jan Buchholz, Maike Taddiken, Markus Fehrenz, Shaden Baradie, Dirk Wübben, Markus Breitbach
2024A Hardware Accelerator for Quantile Estimation of Network Packet Attributes.
Carolina Gallardo-Pavesi, Yaime Fernández, Javier E. Soto, Cecilia Hernández, Miguel E. Figueroa
2024A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications.
Arvin Delavari, Faraz Ghoreishy, Hadi Shahriar Shahhoseini, Sattar Mirzakuchaki
2024A Suite of Processors to Explore CHERI-RISC-V Micro Architecture.
Peter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore
2024APEnetX: A Custom NIC for Cluster Interconnects.
Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Cristian Rossi, Francesco Simula, Piero Vicini
2024AUTOSAR AP and ROS 2 Collaboration Framework.
Ryudai Iwakami, Bo Peng, Hiroyuki Hanyu, Tasuku Ishigooka, Takuya Azumi
2024Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+.
Alejandro Serrano-Cases, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
2024Achieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA.
Jonas Ney, Norbert Wehn
2024Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers.
Bram Van Bolderik, Souradip Sarkar, Vlado Menkovski, Sonia M. Heemstra de Groot, Manil Dev Gomony
2024An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery.
Cornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju
2024An HLS Algorithm for the Direct Synthesis of Complex Control Flow Graphs Into Finite State Machines with Implicit Datapath.
Jean-Christophe Le Lann
2024Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems.
Laura Quintana, Carlos Vega, Raquel León, Guillermo V. Socorro-Marrero, Samuel Ortega, Gustavo M. Callicó
2024Assessment of the Performance of a Commercial Spectral Sensor for Portable and Cost-Effective Multispectral Applications.
Antonio J. Pérez-Ávila, Miguel A. Mesa-Simón, Antonio Martínez-Olmos, Alberto J. Palma, Nuria López-Ruiz
2024Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs.
Matthias Stammler, Florian Schade, Jürgen Becker
2024Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs.
Shree Harish S, Debapriya Basu Roy
2024CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video.
Daniel Suárez, Víctor Fernández, Héctor Posadas
2024Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure.
Can Aknesil, Elena Dubrova
2024Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs.
Noïc Crouzet, Thomas Carle, Christine Rochange
2024Counter Power Leakage for Frequency Extraction of Ring Oscillators in ROPUF.
Ondrej Stanícek, Filip Kodýtek, Róbert Lórencz
2024DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge.
Ensieh Aliagha, Najdet Charaf, Nitin Krishna Venkatesan, Diana Göhringer
2024DSL-Based SNN Accelerator Design Using Chisel.
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2024Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation.
Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das
2024Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, Antonio J. Acosta
2024Digital Twins Benefits and Challenges from Intelligent Motion Control Point of View.
Matias Vierimaa, Mikko Heiskanen, Sajid Mohamed, Hans Kuppens
2024Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations.
Georgios Anagnostopoulos, Nikolaos Zompakis, Sotirios Xydis
2024Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator.
Federico Nicolás Peccia, Svetlana Pavlitska, Tobias Fleck, Oliver Bringmann
2024Event Monitor Validation in High-Integrity Systems.
Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J. Cazorla
2024Event-Based Vision on FPGAs - a Survey.
Tomasz Kryjak
2024Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification.
Julio Costella Vicenzi, Guilherme Korol, Michael G. Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck
2024Exploration of Custom Floating-Point Formats: A Systematic Approach.
Saba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis, Ahmed Hemani
2024Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow.
Kévin Quénéhervé, William Pensec, Philippe Tanguy, Rachid Dafali, Vianney Lapôtre
2024External Memory Protection on FPGA-Based Embedded Systems.
João Carlos Resende, Aleksandar Ilic, Ricardo Chaves
2024FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing.
Domenico Ragusa, Antonio J. Rodríguez-Almeida, Marco Gazzoni, Emanuele Torti, Elisa Marenzi, Himar Fabelo, Gustavo M. Callicó, Francesco Leporati
2024FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar.
Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf
2024Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine.
Gabriela Mystkowska, Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci
2024HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework.
Saketh Gajawada, Dantu Nandini Devi, Madhav Rao
2024HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images.
Marco Gazzoni, Emanuele Torti, Elisa Marenzi, Giovanni Danese, Francesco Leporati
2024HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost.
Bailian Sun, Mohamed Hassan
2024Hardware Acceleration of Capsule Networks for Real-Time Applications.
Maryam Hemmati, Earlene Starling Babette, Julia Shan, Morteza Biglari-Abhari, Smaïl Niar
2024Hardware Generators with Chisel.
Martin Schoeberl, Hans Jakob Damsgaard, Luca Pezzarossa, Oliver Keszöcze, Erling Rennemo Jellum
2024Hardware-level Access Control and Scheduling of Shared Hardware Accelerators.
Cornelia Wulf, Sergio A. Pertuz, Diana Göhringer
2024High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs.
Yan Chen, Kiyofumi Tanaka
2024How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller.
Lukás Danêk, Martin Novotný
2024Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash Algorithm.
Matús Oleksák, Vojtech Miskovský
2024In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization.
Paola Vitolo, Gian Domenico Licciardo, Danilo Pau, Rosalba Liguori, Luigi Di Benedetto, Alfredo Rubino
2024Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches.
Ján Mach, Lukás Kohútka, Pavel Cicák
2024Integrated Mapping and Scheduling Optimization with Genetic Algorithms Based on a Novel Encoding Scheme.
Zhifang Sun, Shengjie Jin, Jinxue Duan, Junqiang Jiang, Zebo Peng
2024Inter-Band Movement Compensation Method for Hyperspectral Images Based on Spectral Scanning Technology.
Nerea Marquez-Suarez, Carlos Vega, Raquel León, Gustavo M. Callicó
2024Investigation of Commercial Off-The-Shelf ReRAM Modules for Use as Runtime-Accessible TRNG.
Tolga Arul, Nico Mexis, Aleena Elsa George, Florian Frank, Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser
2024LeQC-At: Learning Quantization Configurations During Adversarial Training for Robust Deep Neural Networks.
Siddharth Gupta, Salim Ullah, Akash Kumar
2024Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study.
Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner
2024Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA.
Daniel Enériz, Antonio J. Rodríguez-Almeida, Himar Fabelo, Gustavo M. Callicó, Nicolás Medrano, Belén Calvo
2024Multiprotocol Middleware Translator for IoT.
Bernando Cabral, Ricardo Venâncio, Pedro Costa, Tiago Fonseca, Luis Lino Ferreira, Ricardo Severino, António Barros
2024Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models.
Mounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker
2024PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection.
Sima Sinaei, Mohammadreza Mohammadi, Rakesh Shrestha, Mina Alibeigi, David Eklund
2024Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory.
Shima Hosseinzadeh, Suzanne Lancaster, Amirhossein Parvaresh, Cláudia Silva, Dietmar Fey
2024Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18.
Zhuoer Li, Sébastien Bilavarn
2024PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data.
Dominika Przewlocka-Rus, Tomasz Kryjak, Marek Gorgon
2024Precision and Power Efficient Piece-Wise-Linear Implementation of Transcendental Functions.
Kanish R, Omkar G. Ratnaparkhi, Madhav Rao
2024REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AI.
Andreas Brokalakis, Iakovos Mavroidis, Konstantinos Georgopoulos, Pavlos Malakonakis, Konstantinos Harteros, Dimitris Andronikou, Yannis Galanomatis, Charalampos Savvakos, Grigorios Chrysos, Sotiris Ioannidis, Ioannis Papaefstathiou
2024SAND5G - Security Assessments for Networks and Services in 5G Networks.
Aimilia Bantouna, Kostas Lampropoulos, Omar Qaise, Andreas Stamoulis, Paris Kitsos, Kostas Poulios, Lampros Raptis, Christos Tranoris
2024SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth.
Luca Müller, Rolf Drechsler
2024Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment.
William Pensec, Vianney Lapôtre, Guy Gogniat
2024Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization.
Philipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2024Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical Threats.
Quentin Jayet, Christine Hennebert, Yann Kieffer, Vincent Beroulle
2024SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems.
Luca Zulberti, Andrea Monorchio, Matteo Monopoli, Gabriela Mystkowska, Pietro Nannipieri, Luca Fanucci
2024SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs.
Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy
2024Streamlined Models of CMOS Image Sensors Carbon Impacts.
Olivier Weppe, Jérôme Chossat, Thibaut Marty, Jean-Christophe Prévotet, Maxime Pelcat
2024Studying the Degradation of Propagation Delay on FPGAs at the European XFEL.
Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2024Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists.
Rens Baeyens, Max Cornilly, Dennis Laurijssen, Ron Clijsen, Jean-Pierre Baeyens, Jan Steckel, Walter Daems
2024TAP: Task-Aware Profiling on Integrated Systems.
Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
2024Teaching Agile Hardware Design with Chisel.
Scott Beamer
2024The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things.
Jakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp
2024The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators.
Alejandro J. Calderón, Aitor Amonarriz, Mar Hernández, Leonidas Kosmidis, Jannis Wolf, Marc Solé Bonet, Matina Maria Trompouki, Mikel Segura, Peio Onaindia
2024The TEXTAROSSA Project: Cool all the Way Down to the Hardware.
Antonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo
2024Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project.
Hassan Aboushady, Noemie Beringuier-Boher, Kelly Burke, Philippe Dallemagne, Mario De Biase, Manuel Di Frangia, Virginie Deniau, Enrico Ferrari, Christophe Gaquière, Dominique Morche, Fabio Patrone, Stefano Pesci, Luigi Pomante, Andries Stam, Vincenzo Stornelli, Haralampos-G. Stratigopoulos, Mottaqiallah Taouil, Emmanuel Vaumorin, Jonathan Villain, Sander Steeghs
2024Two's Complement: Monitoring Software Control Flow Using Both Power and Electromagnetic Side Channels.
Michael Amar, Lojenaa Navanesan, Asanka P. Sayakkara, Yossi Oren
2024ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic.
Franz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf