DSD C

104 papers

YearTitle / Authors
2007A DRAM Precharge Policy Based on Address Analysis.
Chiyuan Ma, Shuming Chen
2007A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture.
Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, Reiner Peters
2007A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems.
Federico Baronti, Francesco Lenzi, Roberto Roncella, Roberto Saletti
2007A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length Partitioning.
Nadia Nedjah, Luiza de Macedo Mourelle
2007A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor.
Matthew Marshall, Gordon Russell
2007A New Class of Cellular Automata.
Hosna Jabbari, Jon C. Muzio, Lin Sun
2007A New Framework for Design and Simulation of Complex Hardware/Software Systems.
Carlo Brandolese, D. Crespi, Laura Frigerio, Fabio Salice
2007A Proposal of New Join Operators for Sensor Network Databases.
Seungjae Lee, Changhwa Kim, Sangkyung Kim
2007A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography.
Santosh Ghosh, Monjur Alam, Indranil Sengupta, Dipanwita Roy Chowdhury
2007A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator.
Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
2007A Serial Logarithmic Number System ALU.
Mark G. Arnold, Panagiotis D. Vouzis
2007A Sliced Coprocessor for Native Clifford Algebra Operations.
Silvia Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile
2007A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.
J. V. R. Ravindra, M. B. Srinivas
2007A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications.
Matthew D'Souza, Konstanty Bialkowski, Adam Postula, Montserrat Ros
2007A resource optimized Processor Core for FPGA based SoCs.
Gerald Hempel, Christian Hochberger
2007Adaptive Distance Estimation and Localization in WSN using RSSI Measures.
Abdalkarim Awad, Thorsten Frunzke, Falko Dressler
2007Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis.
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
2007Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.
Scott Miller, Mihai Sima, Michael McGuire
2007An Efficient BIST Scheme for Non-Restoring Array Dividers.
Haridimos T. Vergos
2007An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation.
Serkan Oktem, Ilker Hamzaoglu
2007An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding.
Esra Sahin, Ilker Hamzaoglu
2007An Embedded Implementation of the Microsoft Common Language Infrastructure.
Joseph C. Libby, Kenneth B. Kent
2007An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
Mohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram
2007An Implementation of an Address Generator Using Hash Memories.
Tsutomu Sasao, Munehiro Matsuura
2007An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits.
Elham K. Moghaddam, Shaahin Hessabi
2007An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2007Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits.
Sharon Van Schaick, Kenneth B. Kent
2007Application-Specific Topology Design Customization for STNoC.
Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola
2007Architecture Exploration of 3D Video Recorder Using Virtual Platform Models.
Matti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen
2007Architecture of a Small Low-Cost Satellite.
Dante Del Corso, Claudio Passerone, Leonardo Maria Reyneri, Claudio Sansoè, Marco Borri, Stefano Speretta, Maurizio Tranchero
2007Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems.
Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2007Component-Based Hardware/Software Co-Simulation.
Ping Hang Cheung, Kecheng Hao, Fei Xie
2007Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs.
Andrzej Krasniewski
2007Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri net.
Katsumi Wasaki, Toshiaki Harai, Tamotsu Hayashi, Ken-ichi Arai
2007Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction.
Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold
2007Decoupling of Computation and Communication with a Communication Assist.
Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen
2007Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007Design Without Borders.
Jan M. Rabaey
2007Design and Implementation of a 50MHZ DXT CoProcessor.
Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi
2007Design and Implementation of a 90nm Low bit-rate Image Compression Core.
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
2007Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer.
Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra
2007Energy Based Design Space Exploration of Multiprocessor VLIW Architectures.
Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan
2007Error-Aware Design.
Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng
2007Evaluating Energy Consumption in Wireless Sensor Networks Applications.
Agustin Barberis, Leonardo Barboni, Maurizio Valle
2007Evaluating the Model Accuracy in Automated Design Space Exploration.
Kalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen
2007Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism.
Peter Poplavko, Twan Basten, Jef L. van Meerbergen
2007Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor.
Volker Hampel, Peter Sobe, Erik Maehle
2007Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.
Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007FATTY: A Reliable FAT File System.
Alei Liang, Kejia Liu, Xiaoyong Li, Haibing Guan
2007FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications.
Jinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou
2007FPGA-based Road Traffic Videodetector.
Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo
2007FPGA/DSP-based Configurable Multi-Channel Counter.
Daniele Audino, Federico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti
2007Fault Diagnosis in Integrated Circuits with BIST.
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen
2007Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey.
Falk Salewski, Adam Taylor
2007Fault Injection Techniques and their Accelerated Simulation in SystemC.
Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
2007Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures.
Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel
2007Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi
2007Functional Verification of RTL Designs driven by Mutation Testing metrics.
Youssef Serrestou, Vincent Beroulle, Chantal Robach
2007General Digit-Serial Normal Basis Multiplier with Distributed Overlap.
Martin Novotný, Jan Schmidt
2007GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.
Christoph Puttmann, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
2007Graph Matching Constraints for Synthesis with Complex Components.
Ana Fuentes Martinez, Krzysztof Kuchcinski
2007Hierarchical Identification of Untestable Faults in Sequential Circuits.
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus
2007High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.
Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
2007Hybrid BIST Optimization Using Reseeding and Test Set Compaction.
Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar
2007Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy.
Mikael Millberg, Axel Jantsch
2007Latency Minimization for Synchronous Data Flow Graphs.
Amir Hossein Ghamarian, Sander Stuijk, Twan Basten, Marc Geilen, Bart D. Theelen
2007Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes.
Giuseppe Gentile, Massimo Rovini, Luca Fanucci
2007MPSoC memory optimization for digital camera applications.
Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin
2007Merge Logic for Clustered Multithreaded VLIW Processors.
Manoj Gupta, Fermín Sánchez, Josep Llosa
2007NoC Topologies Exploration based on Mapping and Simulation Models.
Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli
2007Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip.
Pekka Rantala, Jouni Isoaho, Hannu Tenhunen
2007OOCE: Object-Oriented Communication Engine for SoC Design.
Jesús Barba, Fernando Rincón, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López
2007On Complexity of Internal and External Equivalence Checking.
Eugene Goldberg, Kanupriya Gulati
2007On network-on-chip comparison.
Erno Salminen, Ari Kulmala, Timo D. Hämäläinen
2007On the Construction of Small Fully Testable Circuits with Low Depth.
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2007On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.
Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo
2007On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology.
David Roberts, Nam Sung Kim, Trevor N. Mudge
2007On-Chip Verification of NoCs Using Assertion Processors.
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007Online Protocol Testing for FPGA Based Fault Tolerant Systems.
Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka
2007P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications.
Ismail Assayad, Sergio Yovine
2007Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor.
Johann Großschädl, Stefan Tillich, Alexander Szekely
2007Power Estimation of Time Variant SoCs with TAPES.
Andreas Lankes, Thomas Wild, Johannes Zeppenfeld
2007Proving Completeness of Properties in Formal Verification of Counting Heads for Railways.
Sebastian Kinder, Rolf Drechsler
2007Pseudo-Random Pattern Generator Design for Column-Matching BIST.
Petr Fiser
2007RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip.
Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch
2007Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware.
Moonvin Song, Sang Hoon Hong, Yunmo Chung
2007Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.
Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
2007Safety and Security-driven Design of Networked Embedded Systems.
Miroslav Svéda, Roman Trchalík
2007Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment.
Christian J. Hescott, Drew C. Ness, David J. Lilja
2007Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture.
Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
2007Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.
Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami
2007Semiconductor and EDA Challenges: Still Lots To Solve!
Chi-Foon Chan
2007Short Distance Wireless, Dense Networks, and Their Opportunities.
Jan M. Rabaey, Yuen-Hui Chee, David Chen, Luca De Nardis, Simone Gambini, Davide Guermandi, Michael Mark, Nathan Pletcher
2007Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.
Kolin Paul, Joël Porquet, Josep Llosa
2007Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices.
Alex Janek, Christoph Trummer, Christian Steger, Reinhold Weiss, Josef Preishuber-Pfluegl, Markus Pistauer
2007Streaming consistency: a model for efficient MPSoC design.
Jan Willem van den Brand, Marco Bekooij
2007Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany
2007Test Controller Synthesis Constrained by Circuit Testability Analysis.
Richard Ruzicka, Josef Strnadel
2007Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties.
Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek
2007The Criteria of Functional Delay Test Quality Assessment.
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
2007The importance of At-Speed Scan Testing: an industrial experience.
Federico Baronti, Roberto Roncella, Roberto Saletti, Paolo D'Abramo, L. Di Piro, H. Fabian, M. Giardi
2007Timing- / Power-Optimization for Digital Logic Based on Standard Cells.
Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera
2007Toggle Equivalence Preserving (TEP) Logic Optimization.
Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri
2007Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring.
Mladen Berekovic