DSD C

68 papers

YearTitle / Authors
2001A Comparison of Five Different Multiprocessor SoC Bus Architectures.
Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III
2001A Design Methodology for High Performance IC's: Wireless Broadband Radio Baseband Case Study.
Volker Aue, Johannes Kneip, Matthias Weiss, Michael Bolle, Gerhard P. Fettweis
2001A Global Routing Technique for Wave-Steering Design Methodology.
Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
2001A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines.
Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss
2001A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition.
F. Lesser, Jan de Cuveland, Volker Lindenstruth, C. Reichling, R. Schneider, M. W. Schulz
2001A Multi-Lingual Synthesis and Verification Environment.
George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos
2001A Multiple Context Reconfigurable Functional Unit.
Michael C. Miller, Daniel Tabak
2001A Run-Time Support Environment for Reconfigurable Systems.
L. Bubb, Martyn Edwards, Peter Green, C. Pimlott, K. Rees, M. Stewart, A. Taylor, M. Vakondios, J. Yates
2001A Wireless Interconnection Network for Parallel Processing.
Jacek Marczynski, Daniel Tabak
2001Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems.
Pramote Kuacharoen, Tankut Akgul, Vincent John Mooney, Vijay K. Madisetti
2001An Approach to Minimization of Decision Diagrams .
Pawel Kerntopf
2001An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation.
Andrzej Ryszko, Kazimierz Wiatr
2001An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code.
Øyvind Strøm, Einar J. Aas
2001An Improved Input-Output Encoding Approach for Functional Decomposition.
Muthukumar Venkatesan
2001Application of Decision-Making Method for Architecture Selection of ADSL Modem.
Juha-Pekka Soininen, Sandrine Boumard, Tommi Salminen, Hannu Heusala
2001Applying Caching to Two-Level Adaptive Branch Prediction.
Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan
2001Applying Formal Verification with Protocol Compiler.
Christian Stangier, Ulrich Holtmann
2001Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition.
Chichyang Chen, Liang-An Chen, Jih-Ren Cheng
2001Combining Languages in Embedded System Design.
Rolf Ernst
2001Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques.
Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
2001Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations.
Iouliia Skliarova, António de Brito Ferrari
2001Design of a Faithful LNS Interpolator.
Mark G. Arnold
2001Dynamic Branch Prediction Using Neural Networks.
Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan
2001Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures.
Lech Józwiak, Artur Chojnacki
2001Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland
2001Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing.
Andrzej Krasniewski
2001Evaluation of Temporal Formulas Based on "Checking by Spheres".
Wiktor B. Daszczuk
2001Experimental Evaluation of CPU Performance Features.
Janusz Sosnowski, Rafal Jurkiewicz, J. Nowicki
2001FPGA Based Controller for Heterogeneous Image Processing System.
Marek Gorgon, Jaromir Przybylo
2001FPGA Implementation of Addition as a Part of the Convolution.
Ernest Jamro, Kazimierz Wiatr
2001FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation.
José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
2001Fast Test Cost Calculation for Hybrid BIST in Digital Systems.
Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
2001Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis.
Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
2001Fundamentals of Reversible Logic and Computing.
Marek A. Perkowski, Pawel Kerntopf
2001Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution.
Ernest Jamro, Kazimierz Wiatr
2001Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
2001Header Compression in Handel-C - An Internet Application and a New Design Language.
Kjell Torkelsson, Johan Ditmar
2001Hierarchical Modeling and Verification of Embedded Systems.
Luis Alejandro Cortés, Petru Eles, Zebo Peng
2001High-Performance Floating Point Divide.
Albert A. Liddicoat, Michael J. Flynn
2001Improving Single-Thread Fetch Performance on a Multithreaded Processor.
Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque
2001Interconnect-Driven Short-Circuit Power Modeling.
Daniel Eckerbert, Per Larsson-Edefors
2001Level Assignment for Displaying Combinational Logic.
Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
2001Minimization of OPKFDDs Using Genetic Algorithms.
Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler
2001On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.
Enrique San Millán, Luis Entrena, José Alberto Espejo
2001On the Use of Mutations in Boolean Minimization.
Petr Fiser, Jan Hlavicka
2001Optimisation of PPMC Model for Hardware Implementation.
Claudia Feregrino-Uribe, S. R. Jones
2001Pipelined Genetic Architecture with Fitness on the Fly.
Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz
2001Pipelining Considerations for an FPGA Case.
Oswaldo Cadenas, Graham M. Megson
2001Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis.
Giuseppe Coldani, Giovanni Danese, Roberto Gandolfi, P. Ghidetti, Francesco Leporati, Remo Lombardi
2001Practical Aspects of Logic Synthesis Based on Functional Decomposition.
Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski
2001Reconfigurable Computing at Xilinx.
Steven A. Guccione
2001Reconfigurable Computing: A New Business Model and its Impact on SoC Design.
Reiner W. Hartenstein
2001Regular Realization of Symmetric Functions Using Reversible Logic.
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
2001Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor.
Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif
2001Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments.
Pawel Tomaszewicz, Mariusz Rawski
2001Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell.
Mikael M. Nordman, Wojciech E. Kozlowski, Olavi Vähämäki
2001Synchronizing a High-Speed SIMD Processor Array.
Stefan Lund, Lars Bengtsson
2001Synthesis of ASM-based Self-Checking Controllers.
Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky
2001Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming.
Krzysztof Kuchcinski, Christophe Wolinski
2001Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines.
Valeri Solovjev
2001System Modeling in the COSMA Environment.
Wiktor B. Daszczuk, Waldemar Grabski, Jerzy Miescicki, Jacek Wytrebowicz
2001Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices.
Vladimir Hahanov, Anna Babich
2001Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing.
Simon Leung, Adam Postula, Ahmed Hemani
2001Timing Driven Wiring on an Advanced Microprocessor.
Paul Kartschoke, Stephen F. Geissler
2001Traffic Scheduling Coprocessor with Schedulability Analysis Capability.
Ernesto Martins, José Alberto Fonseca
2001Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis.
Krzysztof S. Berezowski
2001Two-Criterial Constraint-Driven FSM State Encoding for Low Power.
Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
2001Very High (Over 40 Gb/s) Speed Circuits for Optical Communications - Design Methodolgy and Application Examples.
Agnieszka Konczykowska