| 2025 | 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2025, Lyon, France, May 5-7, 2025 |
| 2025 | A Survey on Automatic Assertion Miners. Mohammad Reza Heidari Iman, Giorgio Di Natale, Katell Morin-Allory |
| 2025 | A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. Amir Hossein Hadipour, Atousa Jafari, Muhammad Awais, Marco Platzner |
| 2025 | Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching. Francesco Gagliardi, Michele Dei |
| 2025 | An Innovative Data Mining Technique for Automatic Anomaly Detection in Physical Unclonable Functions. Mohammad Reza Heidari Iman, Sergio Vinagrero Gutierrez, Elena-Ioana Vatajelu, Giorgio Di Natale |
| 2025 | Analysis and Mitigation of Soft-errors in GPU-accelerated Hyperspectral Image Classifiers. Sergiu-Mohamed Abed, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Gianluca De Lucia, Marco Lapegna, Matteo Sonza Reorda |
| 2025 | Automatic generation of input-aware approximate arithmetic circuits. Mario Barbareschi, Salvatore Barone, Alberto Bosio, Bastien Deveautour, Ali Piri, Marcello Traiola |
| 2025 | Boosting SW Development Efficiency with Function Lifetime Diagrams. Christoph Hazott, Daniel Große |
| 2025 | Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators. Obed M. Mogaka, Håkan Forsberg, Masoud Daneshtalab |
| 2025 | Comparative Study of Safety and Security-Protected AES Designs. Daniel Thirion, Jean-Marc Daveau, Valentin Egloff, David Hély, Vincent Beroulle, Philippe Roche |
| 2025 | Controllability-Based Circuit Similarity Estimation. Michal Zácek, Petr Fiser |
| 2025 | CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | DEAR-CNN: Data-Efficient Assessment of Resiliency in Convolutional Neural Networks. Nicolò Bellarmino, Alberto Bosio, Riccardo Cantoro, Annachiara Ruospo, Ernesto Sánchez |
| 2025 | Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables. Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn |
| 2025 | Domain-Specific Design Abstraction with Emphasis on Neural Networks. Maryam Rajabalipanah, Zahra Hojati, Zahra Jahanpeima, Zainalabedin Navabi |
| 2025 | Duality and resonance in RLC-circuits. Exact formulas for phase, amplitude resonance and bandwidth. Daniel Blokhin |
| 2025 | Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices. Mounika Vaddeboina, Alper Yilmazer, Wolfgang Ecker |
| 2025 | Implementation of Dynamic SISD-SIMD Integer Dividers. Gianluca Radi, Ares Tahiraga, Robert Kunzelmann, Ties Jan Henderikus Kluter, Wolfgang Ecker |
| 2025 | Inference Energy Analysis in Context of Hardware-Aware NAS. Michal Pinos, Jan Klhufek, Vojtech Mrazek, Lukás Sekanina |
| 2025 | LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors. Weiyan Zhang, Muhammad Hassan, Rolf Drechsler |
| 2025 | Lazy Man's Resynthesis For Glitching-Aware Power Minimization. Andrea Costamagna, Xiaoqing Xu, Giovanni De Micheli, Dino Ruic |
| 2025 | Mitigating DoS Attacks on CAN: A Priority-Raise Approach and Its Timing Analysis. Mingqing Zhang, Alejandro Masrur |
| 2025 | Modeling and Simulation of Thermal Faults in Batteries for Enhanced Safety. Francesco Tosoni, Sara Vinco, Franco Fummi |
| 2025 | RL-Agent-based Early-Exit DNN Architecture Search Framework. Mahdi Taheri, Parth Patne, Natalia Cherezova, Ali Mahani, Christian Herglotz, Maksim Jenihhin |
| 2025 | River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. Till Schnittka, Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors. Elia Lazzeri, Matteo Colella, Gianluca Furano, Luca Cassano |
| 2025 | Stratified sampling: fast estimation of quantization effects on DNN. Quentin Milot, Mickaël Dardaillon, Daniel Ménard |
| 2025 | Study of an OPTO-ASIC for a Functionally Safe Speed Sensor Using the Spatial Frequency Filter Method. Frank Wasinski, Werner Bonath, Ubbo Ricklefs, Michael Schwarz, Josef Börcsök |
| 2025 | Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler |
| 2025 | Tunable Voltage Reference circuit in a standard 65nm CMOS technology. Róbert Ondica, David Maljar, Miroslav Potocný, Daniel Arbet, Viera Stopjaková |
| 2025 | Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. Claire Fenouillet-Béranger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudouin Martineau, Marie Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet |