DDECS C

36 papers

YearTitle / Authors
201922nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019
2019A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider.
Hwann-Kaeo Chiou, Wei-Min Sung
2019A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System.
Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng
2019A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network.
Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman
2019Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic.
Roman Vrana, Jan Korenek, David Novak
2019Analyzing and Optimizing the Dummy Rounds Scheme.
Stanislav Jerabek, Jan Schmidt
2019Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers.
Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen
2019Automated Integration of Dynamic Power Management into FPGA-Based Design.
Michal Skuta, Dominik Macko
2019Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter.
Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz
2019Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts.
Muhammad Tanweer, Kari A. I. Halonen
2019Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems.
Ching-Hwa Cheng, Tang-Chieh Liu
2019Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test.
F. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli, Gulio Zoppi
2019Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures.
Martin Stáva
2019Encryption-Based Secure JTAG.
Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2019FPGA-based SIFT implementation for wearable computing.
Attila Fejér, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger
2019Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines.
Vlad Muresan, Mihail Abrudean
2019Fault-Aware Performance Assessment Approach for Embedded Networks.
Jan Malburg, Karl Janson, Jaan Raik, Frank Dannemann
2019From Constraints to Tape-Out: Towards a Continuous AMS Design Flow.
Andreas Krinke, Tilman Horst, Georg Gläser, Martin Grabmann, Tobias Markus, Benjamin Prautsch, Uwe Hatnik, Jens Lienig
2019Generic Error Localization for the Electronic System Level.
Sebastian Pointner, Pablo González de Aledo, Robert Wille
2019Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing.
Amin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
2019Hardware and control design of a ball balancing robot.
Ioana Lal, Marius Nicoara, Alexandru Codrean, Lucian Busoniu
2019Hash-based Pattern Matching for High Speed Networks.
Tomas Fukac, Jan Korenek
2019High side power MOSFET switch driver for a low-power AC/DC converter.
Miroslav Potocný, Juraj Brenkus, Viera Stopjaková
2019Hybrid on-line self-test architecture for computational units on embedded processor cores.
Andrea Floridia, Gianmarco Mongano, Davide Piumatti, Ernesto Sánchez
2019Implementation of FPGA-based Accelerator for Deep Neural Networks.
Tsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu
2019Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology.
Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy
2019Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems.
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
2019Modular Data Link Layer Processing for THz communication.
Lukasz Lopacinski, Mohamed Hussein Eissa, Goran Panic, Alireza Hasani, Rolf Kraemer
2019New categories of Safe Faults in a processor-based Embedded System.
Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2019Nonlinear Compression Codes Used In IC Testing.
Ondrej Novák
2019On the in-field test of the GPGPU scheduler memory.
Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2019Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI's Components using RAD-THERM TCAD Subsystem.
Konstantin O. Petrosyants, Maxim V. Kozhukhov, Dmitry Popov
2019Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430.
Karel Szurman, Zdenek Kotásek
2019Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime.
Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang
2019Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology.
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková
2019Using Voters May Lead to Secret Leakage.
Jan Belohoubek, Petr Fiser, Jan Schmidt