| 2017 | 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017 Manfred Dietrich, Ondrej Novák |
| 2017 | A 50 GHz SiGe BiCMOS active bandpass filter. Saurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha |
| 2017 | A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging. Norbert Druml, Christoph Ehrenhöfer, Walter Bell, Christian Gailer, Hannes Plank, Thomas Herndl, Gerald Holweg |
| 2017 | A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology. Michal Wolodzko, Wieslaw Kuzmicz |
| 2017 | A novel architecture for LZSS compression of configuration bitstreams within FPGA. Radek Isa, Jirí Matousek |
| 2017 | A scalable technique to identify true critical paths in sequential circuits. Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik |
| 2017 | An analysis of the operation and SET robustness of a CMOS pulse stretching circuit. Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer |
| 2017 | An efficient physical design of fully-testable BDD-based circuits. Andreas Rauchenecker, Robert Wille |
| 2017 | Analog front-end for precise human body temperature measurement. Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz |
| 2017 | Are XORs in logic synthesis really necessary? Ivo Hálecek, Petr Fiser, Jan Schmidt |
| 2017 | Body biasing for analog design: Practical experiences in 22 nm FD-SOI. Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich |
| 2017 | Cycle-accurate software modeling for RTL verification of embedded systems. Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz |
| 2017 | Design and optimisation of NiTi pressure gauge. Martin Hunek, Zdenek Plíva |
| 2017 | Design for three-dimensional sound processor using high-level synthesis. Saya Ohira, Tetsuya Matsumura |
| 2017 | Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. Matthias Kampmann, Sybille Hellebrand |
| 2017 | Energy-aware application-specific topology generation for 3D Network-on-Chips. Arash Barzinmehr, Suleyman Tosun |
| 2017 | Fault detection and self repair in Hsiao-code FEC circuits. Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus |
| 2017 | Firmware Update Manager: A remote firmware reprogramming tool for low-power devices. Ondrej Kachman, Marcel Baláz |
| 2017 | Formal Design Space Exploration for memristor-based crossbar architecture. Marcello Traiola, Mario Barbareschi, Alberto Bosio |
| 2017 | From online fault detection to fault management in Network-on-Chips: A ground-up approach. Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein |
| 2017 | HLS design of a hardware accelerator for Homomorphic Encryption. Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki |
| 2017 | Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator. Madis Kerner, Kalle Tammemäe |
| 2017 | Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider |
| 2017 | Improving combinational circuit resilience against soft errors via selective resource allocation. Tohid Taghizad Gogjeh Yaran, Suleyman Tosun |
| 2017 | Logic testing with test-per-clock pattern loading and improved diagnostic abilities. Ondrej Novák, Zdenek Plíva |
| 2017 | Mapping abstract and concrete hardware models for design understanding. Tino Flenker, Görschwin Fey |
| 2017 | Mealy-to-moore transformation. Mustafa Ozgul, Florian Deeg, Sebastian M. Sattler |
| 2017 | Measuring metastability using a time-to-digital converter. Thomas Polzer, Florian Huemer, Andreas Steininger |
| 2017 | Novel metrics for Analog Mixed-Signal coverage. Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher |
| 2017 | On hardware-based fault-handling in dynamically scheduled processors. Felix Mühlbauer, Lukas Schröder, Mario Schölzel |
| 2017 | On the robustness of memristor based logic gates. Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui |
| 2017 | Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. Petr Socha, Vojtech Miskovský, Hana Kubátová, Martin Novotný |
| 2017 | PMS2UPF: An automated transition from ESL to RTL power-intent specification. Miroslav Siro, Dominik Macko, Katarína Jelemenská |
| 2017 | Rocket Queue: New data sorting architecture for real-time systems. Lukás Kohútka, Viera Stopjaková |
| 2017 | Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic |
| 2017 | Structure-preserving modeling of safety-critical combinational circuits. Feim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler |
| 2017 | Towards approximation during test of Integrated Circuits. Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio |
| 2017 | Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology. Michal Sovcik, Martin Kovác, Daniel Arbet, Viera Stopjaková |