DDECS C

92 papers

YearTitle / Authors
201114th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011
Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus
2011A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application.
Farhad Goodarzy, Efstratios Skafidas
2011A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology.
Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski
2011A chaos-based pseudo-random bit generator implemented in FPGA device.
Pawel Dabal, Ryszard Pelka
2011A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits.
Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos
2011A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors.
Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2011A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations.
Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz
2011A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs.
Muhammad Aamir Khan, Hans G. Kerkhoff
2011A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring.
Martin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel
2011A wireless ECG sensor node based on Huffman data encoder.
Uros Pesovic, Sinisa Randic, Zoran Stamenkovic
2011Abstract modeling and simulation based selective estimation.
Yaseen Zaidi, Sumit Adhikari, Christoph Grimm
2011Advanced fault tolerant bus for multicore system implemented in FPGA.
Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek
2011Advanced rectifier and driver for analog VU meter.
Martin Pospisilik, Milan Adamek
2011An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator.
Tetsuya Iizuka, Kunihiro Asada
2011An analog perspective on device reliability in 32nm high-κ metal gate technology.
Florian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel
2011An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors.
Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
2011An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform.
Wlodzimierz Wrona, Pawel Duc, Lukasz Barcik, Wojciech Pietrasina
2011Automatic property generation for the formal verification of bus bridges.
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011Behavior of CMOS polymorphic circuits in high temperature environment.
Richard Ruzicka, Václav Simek, Lukás Sekanina
2011Behavioral model of TRNG based on oscillator rings implemented in FPGA.
Knut Wold, Slobodan Petrovic
2011CAD tool for PLL Design.
Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011Characterization of digital cells for statistical test.
Fabian Hopsch, Michael Lindig, Bernd Straube, Wolfgang Vermeiren
2011Communication modelling and synthesis for NoC-based systems with real-time constraints.
Mihkel Tagel, Peeter Ellervee, Thorsten Hollstein, Gert Jervan
2011Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies.
Gábor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjaková
2011Conversion and interfacing techniques for asynchronous circuits.
Markus Ferringer
2011Cost effective scaling to 22nm and below technology nodes.
Andrzej J. Strojwas
2011Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders.
Xuan-Tu Tran, Van-Huan Tran
2011Current sensing methodology for completion detection in self-timed systems.
Lukás Nagy, Viera Stopjaková
2011DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development.
Stefan Farfeleder, Thomas Moser, Andreas Krall, Tor Stålhane, Herbert Zojer, Christian Panis
2011Decomposition of multi-output logic function in Reed-Muller spectral domain.
Stefan Kolodzinski, Edward Hrynkiewicz
2011Decoupling capacitance boosting for on-chip resonant supply noise reduction.
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011Decreasing test time by scan chain reorganization.
Pavel Bartos, Zdenek Kotásek, Jan Dohnal
2011Defect-oriented module-level fault diagnosis in digital circuits.
Sergei Kostin, Raimund Ubar, Jaan Raik
2011Design technology and the cloud.
Raul Camposano
2011Design-for-Test method for high-speed ADCs: Behavioral description and optimization.
Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho
2011Dual use of power lines for data communications in microprocessors.
Vipul Chawla, Dong Sam Ha
2011Dynamic placement applications into Self Adaptive network on FPGA.
Petr Honzík, Jirí Kadlec
2011Effective hash-based IPv6 longest prefix match.
Jiri Tobola, Jan Korenek
2011Efficient diagnostics algorithms for regular computing structures.
Miroslav Manik, Elena Gramatová
2011Error recovery technique for coarse-grained reconfigurable architectures.
Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
2011Failure probability of SRAM-FPGA systems with Stochastic Activity Networks.
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2011Fast just-in-time translated simulator for ASIP design.
Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár
2011Fault injection analysis of transient faults in clustered VLIW processors.
Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda
2011Fault tolerance of SRAM-based FPGA via configuration frames.
Farid Lahrach, Abderrahim Doumar, Eric Châtelet
2011Functional enhancements of TMR for power efficient and error resilient ASIC designs.
Hagen Sämrow, Claas Cornelius, Philipp Gorski, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann
2011Future of EDA: Usual suspect or silent hero for successful semiconductor business?
Jürgen Alt
2011Hardware architecture for packet classification with prefix coloring.
Viktor Pus, Michal Kajan, Jan Korenek
2011Hardware efficient design of Variable Length FFT Processor.
Vinay Gautam, Kailash Chandra Ray, Pauline C. Haddow
2011High performance adaptive sensor interface design through model based estimation of analog non-idealities.
Sumit Adhikari, Muhammad Farooq, Jan Haase, Christoph Grimm
2011High-performance hardware accelerators for sorting and managing priorities.
Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC.
Oliver Stecklina, Frank Vater, Thomas Basmer, Erik Bergmann, Hannes Menzel
2011Implementation of Selective Fault Tolerance with conventional synthesis tools.
Michael Augustin, Michael Gössel, Rolf Kraemer
2011Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm.
Liviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan
2011Increasing the efficiency of analog OBIST using on-chip compensation of technology variations.
Daniel Arbet, Juraj Brenkus, Gábor Gyepes, Viera Stopjaková
2011Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations.
Tsuyoshi Iwagaki, Kewal K. Saluja
2011Influence of parasitic memory effect on single-cell faults in SRAMs.
Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell
2011Introduction to the SystemC AMS extension standard.
Karsten Einwich
2011Low-complexity integrated circuit aging monitor.
Aleksandar Simevski, Rolf Kraemer, Milos Krstic
2011Low-power quadrature VCO design for medical implant communication service.
Jeong-Ki Kim, Jihoon Jeong, Dong Sam Ha, Hyung-Soo Lee
2011Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario.
Carmen Garcia, Antonio Rubio
2011Max-Fill: A method to generate high quality delay tests.
Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz
2011Measurement point selection for in-operation wear-out monitoring.
Urban Ingelsson, Shih-Yen Chang, Erik Larsson
2011Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms.
André Seffrin, Sorin A. Huss
2011Muller C-elements based on minority-3 functions for ultra low voltage supplies.
Hans Kristian Otnes Berge, Amir Hasanbegovic, Snorre Aunet
2011On using a SPICE-like TSTAC™ eFlash model for design and test.
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip.
Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair.
Tobias Koal, Heinrich Theodor Vierhaus
2011Optimization of message encryption for distributed embedded systems with real-time constraints.
Ke Jiang, Petru Eles, Zebo Peng
2011Optimized embedded memory diagnosis.
Mauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi
2011Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications.
Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011Power consumption traces realignment to improve differential power analysis.
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal
2011Precise IPv4/IPv6 packet generator based on NetCOPE platform.
Jirí Matousek, Pavol Korcek
2011Probabilistic equivalence checking based on high-level decision diagrams.
Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2011Proof certificates and non-linear arithmetic constraints.
Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle
2011Receiver OEIC using a bipolar translinear loop.
Artur Marchlewski, Horst Zimmermann, Ingrid Jonak-Auer, Ewald Wachmann
2011Reduction of FPGA resources for regular expression matching by relation similarity.
Vlastimil Kosar, Jan Korenek
2011SAT-based analysis of sensitisable paths.
Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
2011Sample synchronization of multiple multiplexed DA and AD converters in FPGAs.
Thilo Ohlemueller, Markus Petri
2011SiGe BiCMOS platform - baseline technology for More Than Moore process module integration.
Bernd Tillack
2011Small scale energy harvesting - principles, practices and future trends.
Dong S. Ha
2011Software defined radio - design and implementation of complete platform.
Pawel Pawlowski, Adam Dabrowski, Piotr Skrzypek, Piotr Roszak, Andrzej Palejko, Tomasz Walenciak, Mateusz Mor
2011Stacking order impact on overall 3D die-to-wafer Stacked-IC cost.
Mottaqiallah Taouil, Said Hamdioui
2011Statistical analysis of 6T SRAM data retention voltage under process variation.
Elena-Ioana Vatajelu, Joan Figueras
2011TLM protocol compliance checking at the Electronic System Level.
Mohamed Bawadekji, Daniel Große, Rolf Drechsler
2011Test vector overlapping based compression tool for narrow test access mechanism.
Jiri Jenícek, Martin Rozkovec, Ondrej Novák
2011Testing and design-for-testability solutions for 3D integrated circuits.
Krishnendu Chakrabarty
2011Towards an unified IP verification and robustness analysis platform.
David Hély, Vincent Beroulle, Feng Lu, José Ramón García Oya
2011Validation and optimization of TMR protections for circuits in radiation environments.
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
2011Verification of JPEG2000 encoder based on rate and distortion curve analysis.
Damian Modrzyk, Michal Staworko
2011Wireless wafer-level testing of integrated circuits via capacitively-coupled channels.
Dae Young Lee, David D. Wentzloff, John P. Hayes