DDECS C

61 papers

YearTitle / Authors
20090.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area.
Y. C. Chang, Hsuan-Ling Kao, C. H. Kao, C. H. Yang, Jeffrey S. Fu, Nemai C. Karmakar, Li-Chun Chang
20090.5V 160-MHz 260uW all digital phase-locked loop.
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
2009A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS.
Heimo Uhrmann, Franz Schlögl, Kurt Schweiger, Horst Zimmermann
2009A CMOS bio-impedance measurement system.
Alberto Yufera, Adoración Rueda
2009A comprehensive approach for soft error tolerant Four State Logic.
Werner Friesenbichler, Thomas Panhofer, Martin Delvai
2009A fast untestability proof for SAT-based ATPG.
Daniel Tille, Rolf Drechsler
2009A scheme of logic self repair including local interconnects.
Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
2009A symbolic RTL synthesis for LUT-based FPGAs.
Stanislaw Deniziak, Mariusz Wisniewski
2009All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009An SOC platform for ADC test and measurement.
Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann
2009An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.
Florence Azaïs, Yves Bertrand, Michel Renovell
2009An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2009An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.
Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda
2009An on-line testing scheme for repairing purposes in Flash memories.
Olivier Ginez, Jean-Michel Portal, Hassen Aziza
2009An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions.
Stefan Kolodzinski, Edward Hrynkiewicz
2009Analysis and optimization of ring oscillator using sub-feedback scheme.
Hong-Yi Huang, Fu-Chien Tsai
2009Architecture model for approximate palindrome detection.
Tomás Martínek, Jan Vozenilek, Matej Lexa
2009Asynchronous two-level logic of reduced cost.
Igor Lemberski, Petr Fiser
2009BIST assisted wideband digital compensation for MB-UWB transmitters.
Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee
2009Case Study : A class E power amplifier for ISO-14443A.
Elke De Mulder, Wim Aerts, Bart Preneel, Ingrid Verbauwhede, Guy A. E. Vandenbosch
2009Challenges for test and design for test.
Anton Chichkov
2009Cognitive self-adaptive computing and communication systems: Test, control and adaptation.
Abhijit Chatterjee
2009Comparison of different test strategies on a mixed-signal circuit.
Juraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov
2009Comprehensive bridging fault diagnosis based on the SLAT paradigm.
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009Contactless characterization of MEMS devices using optical microscopy.
András Timár, György Bognár
2009Contention-avoiding custom topology generation for network-on-chip.
Stanislaw Deniziak, Robert Tomaszewski
2009Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS.
Georges G. E. Gielen
2009Diagnosis of faulty units in regular graphs under the PMC model.
Miroslav Manik, Elena Gramatová
2009Effective BIST for crosstalk faults in interconnects.
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2009Effective mars rover platform design with Hardware / Software co-design.
Gábor Marosy, Zoltán Kovács, Gyula Horváth
2009Enhanced LEON3 core for superscalar processing.
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz
2009Experience in Virtual Testing of RSD cyclic A/D converters.
Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko
2009Fast congestion-aware timing-driven placement for island FPGA.
Jinpeng Zhao, Qiang Zhou, Yici Cai
2009Forward and backward guarding in early output logic.
Charlie Brej, Doug Edwards
2009Global parametric faults identification with the use of Differential Evolution.
Piotr Jantos, Damian Grzechca, Jerzy Rutkowski
2009Hardware solution of chaos based image encryption.
Jirí Giesl, Ladislav Behal, Karel K. Vlcek
2009High-level symbolic simulation for automatic model extraction.
Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre
2009Improve clock gating through power-optimal enable function selection.
Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou
2009Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition.
Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar
2009Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories.
Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski
2009Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.
Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
2009Low voltage precharge CMOS logic.
Yngvar Berg, Omid Mirmotahari
2009Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS.
Kurt Schweiger, Heimo Uhrmann, Horst Zimmermann
2009MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.
Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz
2009MTPP - Modular Traffic Processing Platform.
Jiri Halak, Sven Ubik
2009Measurement of power supply noise tolerance of self-timed processor.
Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda
2009On the role of the power supply as an entry for common cause faults - An experimental analysis.
Peter Tummeltshammer, Andreas Steininger
2009Optimization concepts for self-healing asynchronous circuits.
Thomas Panhofer, Werner Friesenbichler, Martin Delvai
2009Packet header analysis and field extraction for multigigabit networks.
Petr Kobierský, Jan Korenek, Libor Polcak
2009Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing.
Yiorgos Sfikas, Yiorgos Tsiatouhas
2009Power devices current monitoring using horizontal and vertical magnetic force sensor.
Martin Donoval, Martin Daricek, Juraj Marek, Viera Stopjaková
2009Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic
2009Round-level concurrent error detection applied to Advanced Encryption Standard.
Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan
2009Self-timed full adder designs based on hybrid input encoding.
P. Balasubramanian, David A. Edwards, Charlie Brej
2009Self-timed thermal sensing and monitoring of multicore systems.
Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila
2009Simulation and planning method for on-chip power distribution - An industry perspective.
Qing K. Zhu, Vincent Bars
2009Structural test of programmed FPGA circuits.
Martin Rozkovec, Ondrej Novák
2009Test scheme for switched-capacitor circuits by digital analyses.
Yun-Che Wen
2009The impact of EFSM composition on functional ATPG.
Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa
2009Ultra low-voltage switched current mirror.
Yngvar Berg, Omid Mirmotahari
2009Using 3-valued memory representation for state space reduction in embedded assembly code model checking.
Thomas Reinbacher, Martin Horauer, Bastian Schlich