DDECS C

80 papers

YearTitle / Authors
2007A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs.
Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira
2007A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing.
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
2007A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling.
Dongsoo Kim, Gunhee Han
2007A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System.
Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang
2007A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2007A Mixed Approach for Unified Logic Diagnosis.
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007A Novel Parity Bit Scheme for SBox in AES Circuits.
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2007A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope.
Valeria Sipala, Domenico Lo Presti, Nunzio Randazzo, Luigi Caponetto
2007A Proposal for ASM++ Diagrams.
Santiago de Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal
2007A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection.
Marco Bucci, Raimondo Luzzi
2007About the Efficiency of Real Time Sequences FFT Computing.
Costin Cepisca, Sorin Dan Grigorescu, Mircea Covrig, Horia Andrei
2007Accurately Determining Bridging Defects from Layout.
Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
2007Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization.
Lukas Ruckay, Jiri Nedved
2007An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego
2007An Improved MDCT IP Core Generator with Architectural Model Simulation.
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
2007Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology.
Zhicheng Liang, Makoto Ikeda, Kunihiro Asada
2007Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.
Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
2007Architecture for Highly Reliable Embedded Flash Memories.
Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli
2007Automatic Generation of Circuits for Approximate String Matching.
Tomás Martínek, Otto Fucík, Patrik Beck, Matej Lexa
2007Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.
Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
2007Built in Defect Prognosis for Embedded Memories.
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2007Clockless Implementation of LEON2 for Low-Power Applications.
Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík
2007Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs.
Grzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba
2007Debug Patterns for Efficient High-level SystemC Debugging.
Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald
2007Decomposition of Logic Functions in Reed-Muller Spectral Domain.
Edward Hrynkiewicz, Stefan Kolodzinski
2007Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment.
Pawel Russek, Kazimierz Wiatr
2007Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology.
András Timár, Márta Rencz
2007Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips.
Bartosz Wojciechowski, Tomasz Kowalczyk, Wojciech Sakowski
2007Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates.
Lukás Sekanina
2007Design and Test of Microfluidic Biochips.
Krishnendu Chakrabarty
2007Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.
Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007Designing Time-to-Digital Converter for Asynchronous ADCs.
Dariusz Koscielnik, Marek Miskowicz
2007Determining MOSFET Parameters in Moderate Inversion.
Matthias Bucher, Antonios Bazigos, Wladyslaw Grabinski
2007Developing Virtual ADC Testing Environment in MAPLE.
Petr Struhovský, Ondrej Subrt, Jirí Hospodka, Pravoslav Martínek
2007ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing.
Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz
2007Establishing a New Course in Reconfigurable Logic System Design.
Jim Tørresen, Jorgen Norendal, Kyrre Glette
2007Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization.
Tomasz Golonek, Damian Grzechca, Jerzy Rutkowski
2007Extended Fault Detection Techniques for Systems-on-Chip.
Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda
2007FPGA Implementation of Strongly Parallel Histogram Equalization.
Ernest Jamro, Maciej Wielgosz, Kazimierz Wiatr
2007Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System.
Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová
2007Feasibility of Image Compression in FPGA-based Neural Networks.
Vladimir Havel, Karel K. Vlcek
2007Flip-Flops and Scan-Path Elements for Nanoelectronics.
René Kothe, Heinrich Theodor Vierhaus
2007IP Integration Overhead Analysis in System-on-Chip Video Encoder.
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
2007Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007Instance Generation for SAT-based ATPG.
Daniel Tille, Görschwin Fey, Rolf Drechsler
2007Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.
Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
2007Intrusion Detection System Intended for Multigigabit Networks.
Jan Korenek, Petr Kobierský
2007Layout to Logic Defect Analysis for Hierarchical Test Generation.
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
2007Lightweight Multi-threaded Network Processor Core in FPGA.
Piotr Buciak, Jakub Botwicz
2007Logic Diagnosis and Yield Learning.
Janusz Rajski
2007Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications.
Gyula Bakonyi-Kiss, Zoltán Szucs
2007MEMS Testing by Vibrating Capacitor.
János Mizsei, M. Reggente
2007Manifestation of Precharge Faults in High Speed DRAM Devices.
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
2007March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.
Luigi Dilillo, Bashir M. Al-Hashimi
2007Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy
2007Memory Based Analogue Signal Generation Implementation Issues for BIST.
Thomas O. Shea, Ian Andrew Grout, Jeffrey Ryan
2007Multiple Errors Detection Technique for RAM.
Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik
2007New Strategies for System-Level Design.
Daniel D. Gajski
2007On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.
Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde
2007Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit.
Wlodzimierz Jonca
2007Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters.
Roman P. Bazylevych, Ihor Podolskyy, Lubov Bazylevych
2007Parts Obsolescence Challenges for the Electronics Industry.
Jim Tørresen, Thor Arne Lovland
2007Power Dissipation in Basic Global Clock Distribution Networks.
Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
2007Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability.
Khalil Arshak, Essa Jafer, Christian Ibala
2007Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007
Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino
2007Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic.
Pawel Pawlowski, Adam Dabrowski, Mario Schölzel
2007Prototyping Generators for On-line Test Vector Generation Based on PSL Properties.
Yann Oddos, Katell Morin-Allory, Dominique Borrione
2007Quadrature-Phase Topology of a High Frequency Ring Oscillator.
Ábel Vámos
2007RF Transformer Model Parameters Measurement.
Vytautas Dumbrava, Linas Svilainis
2007Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.
Aristides Efthymiou
2007Resource Constrained Co-synthesis of Self-reconfigurable SOPCs.
Radoslaw Czarnecki, Stanislaw Deniziak
2007Reticle Exposure Plans for Multi-Project Wafers.
Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu
2007SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse.
Fabrício Vivas Andrade, Márcia C. M. Oliveira, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.
2007Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application.
Khalil Arshak, Francis Adepoju, Essa Jafer
2007Test Pattern Compression Based on Pattern Overlapping.
Jiri Jenícek, Ondrej Novák
2007Test Pattern Generator for Delay Faults.
Tomasz Rudnicki, Andrzej Hlawiczka
2007Transition Faults Testing Based on Functional Delay Tests.
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
2007Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
Ireneusz Brzozowski, Andrzej Kos
2007XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.
Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier