DDECS C

79 papers

YearTitle / Authors
2006A Contextual Resources use: a Proof of Concept through the APACHES' Platform.
Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Borin Soares, Altamiro Amadeu Susin
2006A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming.
Zbysek Gajda
2006A Flexible SoPC-based Fault Injection Environment.
Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
2006A Flexible Technique for the Automatic Design of Approximate String Matching Architectures.
Tomás Martínek, Jan Korenek, Otto Fucík, Matej Lexa
2006A Leakage-based Random Bit Generator with On-line Fault Detection.
Marco Bucci, Raimondo Luzzi
2006A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication.
Abid Rashid, Frank H. P. Fitzek, Ole Olsen, Morten Gade, Yannick Le Moullec
2006A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.
Félix Tobajas, Roberto Esper-Chaín, Raúl Regidor, Octavio Santana, Roberto Sarmiento
2006A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns.
André V. Fidalgo, Gustavo R. Alves, José M. Ferreira
2006A New 6-bit Flash A/D Converter Using Novel Two-Step Structure.
Shih-Chang Hsia, Wen-Ching Lee
2006A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters.
Ondrej Subrt, Pravoslav Martínek
2006A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology.
Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda
2006A Switch Supporting Circuit and Packet Switching for On-Chip Networks.
Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu
2006A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description.
Piotr Dziurzanski, Wlodzimierz Bielecki, Konrad Trifunovic, M. Kleszczonek
2006A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.
Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes
2006An Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning.
Pierre-André Mudry, Guillaume Zufferey, Gianluca Tempesti
2006An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem.
Geguang Pu, Jifeng He, Zongyan Qiu
2006Architecture Design for the Context Formatter in the H.264/AVC Encoder.
Grzegorz Pastuszak
2006Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
2006Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language.
Yves Joannon, Vincent Beroulle, Rami Khouri, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro
2006CMOS Testing at the End of the Roadmap: Challenges and Opportunities.
Jaume Segura
2006Can Clock Faults be Detected Through Functional Test?
Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
2006Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts.
Milos Ohlídal, Josef Schwarz
2006Comparing Subtraction-Free and Traditional AMI.
Jirí Bucek, Róbert Lórencz
2006Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee Application.
András Timár, Ábel Vámos, György Bognár
2006Concurrent Testing of Digital Circuits for Advanced Fault Models.
Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar
2006Dependability Computation for Fault Tolerant Reconfigurable Duplex System.
Pavel Kubalík, Radek Dobias, Hana Kubátová
2006Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC.
Jiri Kadlec, Martin Danek
2006Design of a Scalable Asynchronous Dataflow Processor.
Harri Lampinen, Pauli Perälä, Olli Vainio
2006Design-for-Test of Asynchronous Networks-on-Chip.
Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand
2006Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.
Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
2006Die Attach Quality Testing by Fully Contact-less Measurement Method.
György Bognár, Gyula Horváth, Zoltán Szucs, Vladimír Székely
2006Dynamic Decimal Adder Circuit Design by using the Carry Lookahead.
Younggap You, Yong-Dae Kim, Jong Hwa Choi
2006Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits.
Guoyan Zhang, Ronan Farrell
2006Embedded Self Repair by Transistor and Gate Level Reconfiguration.
René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube
2006Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips.
Jirí Jaros, Václav Dvorák
2006FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.
Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
2006FPGA Implementation of a Fast MDCT Algorithm.
Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz
2006FPGA-based Fault Simulator.
Leos Kafka, Ondrej Novák
2006Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip.
Heikki Kariniemi, Jari Nurmi
2006Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage.
F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2006Generation and Propagation of Single Event Transients in CMOS Circuits.
Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt
2006HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration.
Martin Stáva, Ondrej Novák
2006Hardware/Software Based Hierarchical Self Test for SoCs.
René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus
2006How to Improve a Set of Design Validation Data by Using Mutation-based Test.
Youssef Serrestou, Vincent Beroulle, Chantal Robach
2006ISA Based Functional Test Generation with Application to Self-Test of RISC Processors.
V. V. Belkin, S. G. Sharshunov
2006Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen
2006LEON-2: General Purpose Processor for a Wireless Engine.
Zoran Stamenkovic, C. Wolf, Günter Schoof, Jiri Gaisler
2006Lissajous Based Mixed-Signal Testing for N-Observable Signals.
Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
2006Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems.
Eric Armengaud
2006Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs.
Andrzej Krasniewski
2006March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2006Minimization of Large State Spaces using Symbolic Branching Bisimulation.
Ralf Wimmer, Marc Herbstritt, Bernd Becker
2006Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience.
Ketan Paranjape
2006Multiple Valued Counter.
Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg
2006Multiple-Vector Column-Matching BIST Design Method.
Petr Fiser, Hana Kubátová
2006New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits.
Vladislav Nagy, Viera Stopjaková
2006Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography.
Martin Novotný, Jan Schmidt
2006Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules.
Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
2006On the Use of Information Redundancy When Designing Secure Chips.
Régis Leveugle, V. Maingot
2006Optimal Memory Address Seeds for Pattern Sensitive Faults Detection.
S. V. Yarmolik, Bartosz Sokol
2006PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog IC.
Pavol Malosek, Viera Stopjaková
2006PE-ICE: Parallelized Encryption and Integrity Checking Engine.
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet
2006Parallel Memory Architecture for Arbitrary Stride Accesses.
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
2006Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.
Josef Strnadel
2006Probabilistic Testability Analysis and DFT Methods at RTL.
José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira
2006Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006
Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2006Productivity and Code Quality Improvement of Mixed-Signal Test Software by Applying Software Engineering Methods.
Stefan Vock, Ulrich Flogaus, Hans Martin von Staudt
2006ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
Luca Sterpone, Massimo Violante
2006Recognition of DRM Signal in Frequency Domain and Hardware Demands.
Lukas Ruckay
2006Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor.
Aki Penttinen, Rafal P. Jastrzebski, Riku Pöllänen, Olli Pyrhönen
2006SOC Diagnostic Design Using RESPIN Architecture.
Zbynek Mader, Michal Jarkovský
2006Self-refreshing Multiple Valued Memory.
Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg
2006Sensor Powering with Integrated MOS Compatible Solar Cell Array.
Gergely Perlaky, Gábor Mezösi, Imre Zolomy
2006Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology.
Kristian Granhaug, Snorre Aunet
2006Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow.
Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2006Test Considerations about the Structured ASIC Paradigm.
Paolo Bernardi, Michelangelo Grosso
2006Test Scheduling for SoC under Power Constraints.
Jaroslav Skarvada