DATE A

293 papers

YearTitle / Authors
20072007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007
Rudy Lauwereins, Jan Madsen
2007A calculator for Pareto points.
Marc Geilen, Twan Basten
2007A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.
In-Ho Moon, Per Bjesse, Carl Pixley
2007A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays.
Tao Xu, Krishnendu Chakrabarty
2007A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors.
Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
2007A dynamically adaptive DSP for heterogeneous reconfigurable platforms.
Fabio Campi, Antonio Deledda, Matteo Pizzotti, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi, Arseni Vitkovski, Luca Vanzolini
2007A framework for system reliability analysis considering both system error tolerance and component test quality.
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
2007A future of customizable processors: are we there yet?
Laura Pozzi, Pierre G. Paulin
2007A low-SER efficient core processor architecture for future technologies.
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro
2007A multi-core debug platform for NoC-based systems.
Shan Tang, Qiang Xu
2007A new hybrid solution to boost SAT solver performance.
Lei Fang, Michael S. Hsiao
2007A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems.
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
2007A new technique for characterization of digital-to-analog converters in high-speed systems.
Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz
2007A non-intrusive isolation approach for soft cores.
Ozgur Sinanoglu, Tsvetomir Petrov
2007A novel criticality computation method in statistical timing analysis.
Feng Wang, Yuan Xie, Hai Ju
2007A novel technique to use scratch-pad memory for stack management.
Soyoung Park, Hae-woo Park, Soonhoi Ha
2007A one-shot configurable-cache tuner for improved energy and performance.
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
2007A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.
Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø
2007A smooth refinement flow for co-designing HW and SW threads.
Paolo Destro, Franco Fummi, Graziano Pravadelli
2007A sophisticated memory test engine for LCD display drivers.
Oliver Spang, Hans Martin von Staudt, Michael G. Wahl
2007A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou
2007A symbolic methodology for the verification of analog and mixed signal designs.
Ghiath Al Sammane, Mohamed H. Zaki, Sofiène Tahar
2007A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks.
Pawel Gburzynski, Bozena Kaminska, Wladek Olesinski
2007A two-tone test method for continuous-time adaptive equalizers.
Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue
2007ATLAS: a chip-multiprocessor with transactional memory support.
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
2007Abstraction and refinement techniques in automated design debugging.
Sean Safarpour, Andreas G. Veneris
2007Accounting for cache-related preemption delay in dynamic priority schedulability analysis.
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
2007Accurate and scalable reliability analysis of logic circuits.
Mihir R. Choudhury, Kartik Mohanram
2007Accurate temperature-dependent integrated circuit leakage power estimation is easy.
Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang
2007Accurate timing analysis using SAT and pattern-dependent delay models.
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
2007Adaptive power management in energy harvesting systems.
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini
2007An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface.
Phillip Stanley-Marbell, Diana Marculescu
2007An ADC-BiST scheme using sequential code analysis.
Erdem Serkan Erdogan, Sule Ozev
2007An ILP formulation for system-level application mapping on network processor architectures.
Christopher Ostler, Karam S. Chatha
2007An algorithm to minimize leakage through simultaneous input vector control and circuit modification.
Nikhil Jayakumar, Sunil P. Khatri
2007An area optimized reconfigurable encryptor for AES-Rijndael.
Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta
2007An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip.
Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2007An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs.
Jin Cui, Qingxu Deng, Xiuqiang He, Zonghua Gu
2007An efficient code compression technique using application-aware bitmask and dictionary selection methods.
Seok-Won Seong, Prabhat Mishra
2007An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2007Analytical router modeling for networks-on-chip performance analysis.
Ümit Y. Ogras, Radu Marculescu
2007Applications for ubiquitous computing and communications.
2007Architectural leakage-aware management of partitioned scratchpad memories.
Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii
2007Area optimization of multi-cycle operators in high-level synthesis.
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
2007Assessing carbon nanotube bundle interconnect for future FPGA architectures.
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
2007Automatic application specific floating-point unit generation.
Yee Jern Chong, Sri Parameswaran
2007Automatic synthesis of compressor trees: reevaluating large counters.
Ajay Kumar Verma, Paolo Ienne
2007Boosting the role of inductive invariants in model checking.
Gianpiero Cabodi, Sergio Nocco, Stefano Quer
2007Bus access optimisation for FlexRay-based distributed embedded systems.
Traian Pop, Paul Pop, Petru Eles, Zebo Peng
2007Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
2007CARAT: a toolkit for design and performance analysis of component-based embedded systems.
Egor R. V. Bondarev, Michel R. V. Chaudron, Peter H. N. de With
2007CATS: cycle accurate transaction-driven simulation with multiple processor simulators.
Dohyung Kim, Soonhoi Ha, Rajesh Gupta
2007CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions.
Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke
2007Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs.
Hamidreza Hashempour, Fabrizio Lombardi
2007Clock domain crossing fault model and coverage metric for validation of SoC design.
Yi Feng, Zheng Zhou, Dong Tong, Xu Cheng
2007Clock-frequency assignment for multiple clock domain systems-on-a-chip.
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid
2007Compact hardware design of Whirlpool hashing core.
Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen
2007Compositional specification of behavioral semantics.
Kai Chen, Janos Sztipanovits, Sandeep Neema
2007Computing synchronizer failure probabilities.
Suwen Yang, Mark R. Greenstreet
2007Congestion-controlled best-effort communication for networks-on-chip.
Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten
2007Cost-aware capacity optimization in dynamic multi-hop WSNs.
Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen
2007Cyclostationary feature detection on a tiled-SoC.
André B. J. Kokkeler, Gerard J. M. Smit, Thijs Krol, Jan Kuper
2007DFM/DFY: should you trust the surgeon or the family doctor?
Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki
2007DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems.
Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim
2007Data-flow transformations using Taylor expansion diagrams.
Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon
2007Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.
Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters
2007Design challenges at 65nm and beyond.
Andrew B. Kahng
2007Design closure driven delay relaxation based on convex cost network flow.
Chuan Lin, Aiguo Xie, Hai Zhou
2007Design fault directed test generation for microprocessor validation.
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar
2007Design methods for security and trust.
Ingrid Verbauwhede, Patrick Schaumont
2007Design of high-resolution MOSFET-only pipelined ADCs with digital calibration.
Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi
2007Design space exploration of partially re-configurable embedded processors.
Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007Development and industrialisation.
Michel Riffiod, Paul Caspi, Christophe Piala, Jean-Luc Voirin
2007Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow.
Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu
2007Development of on board, highly flexible, Galileo signal generator ASIC.
Louis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries
2007Diagnosis, modeling and tolerance of scan chain hold-time violations.
Ozgur Sinanoglu, Philip Schremmer
2007Distributed power-management techniques for wireless network video systems.
Nicholas H. Zamora, Jung-Chun Kao, Radu Marculescu
2007Double-via-driven standard cell library design.
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin
2007Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
2007Dynamic learning based scan chain diagnosis.
Yu Huang
2007Dynamic power management under uncertain information.
Hwisung Jung, Massoud Pedram
2007Dynamic reconfiguration in sensor networks with regenerative energy sources.
Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh
2007Efficient and scalable compiler-directed energy optimization for realtime applications.
Po-Kuan Huang, Soheil Ghiasi
2007Efficient code density through look-up table compression.
Talal Bonny, Jörg Henkel
2007Efficient computation of the worst-delay corner.
Luís Guerra e Silva, Luís Miguel Silveira, Joel R. Phillips
2007Efficient high-performance ASIC implementation of JPEG-LS encoder.
Markos E. Papadonikolakis, Vasilleios Pantazis, Athanasios Kakarountas
2007Efficient nonlinear distortion analysis of RF circuits.
Dani Tannir, Roni Khazaka
2007Efficient testbench code synthesis for a hardware emulator system.
Ioannis Mavroidis, Ioannis Papaefstathiou
2007Emerging solutions technology and business views for the ubiquitous communication.
Heikki Huomo
2007Enabling certification for dynamic partial reconfiguration using a minimal flow.
Bertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel
2007Energy and execution time analysis of a software-based trusted platform module.
Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007Energy evaluation of software implementations of block ciphers under memory constraints.
Johann Großschädl, Stefan Tillich, Christian Rechberger, Michael Hofmann, Marcel Medwed
2007Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.
Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
2007Energy-efficient real-time task scheduling with task rejection.
Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King
2007Engineering trust with semantic guardians.
Ilya Wagner, Valeria Bertacco
2007Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling.
B. Jang, Y.-B. Kim, Fabrizio Lombardi
2007Estimating functional coverage in bounded model checking.
Daniel Große, Ulrich Kühne, Rolf Drechsler
2007Evaluation of design for reliability techniques in embedded flash memories.
Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli
2007Event driven data processing architecture.
Ingemar Söderquist
2007Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria
2007Experimental validation of a tuning algorithm for high-speed filters.
Gianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Stefano D'Amico, Andrea Baschirotto
2007FPGA-based networking systems for high data-rate and reliable in-vehicle communications.
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci
2007Fast and accurate routing demand estimation for efficient routability-driven placement.
Peter Spindler, Frank M. Johannes
2007Fast memory footprint estimation based on maximal dependency vector calculation.
Qubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsberg, Francky Catthoor, Martin Palkovic
2007Fast positive-real balanced truncation of symmetric systems using cross Riccati equations.
Ngai Wong
2007Fast statistical circuit analysis with finite-point based transistor model.
Min Chen, Wei Zhao, Frank Liu, Yu Cao
2007Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems.
Liliana Cucu, Joël Goossens
2007Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators.
Pengbo Sun, Ying Wei, Alex Doboli
2007Flexible hardware reduction for elliptic curve cryptography in GF(2
Steffen Peter, Peter Langendörfer, Krzysztof Piotrowski
2007Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space.
Jean Botti
2007Formal verification of a pervasive interconnect bus system in a high-performance microprocessor.
Thuyen Le, Tilman Glökler, Jason Baumgartner
2007From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams.
M. Brandenburg, A. Schöllhorn, S. Heinen, Josef Eckmüller, T. Eckart
2007HW/SW implementation from abstract architecture models.
Ahmed Amine Jerraya
2007Hard real-time reconfiguration port scheduling.
Florian Dittmann, Stefan Frank
2007Hardware scheduling support in SMP architectures.
André C. Nácul, Francesco Regazzoni, Marcello Lajolo
2007Heterogeneous systems on chip and systems in package.
Ian O'Connor, Bernard Courtois, Krishnendu Chakrabarty, N. Delorme, M. Hampton, J. Hartung
2007High-level test synthesis for delay fault testability.
Sying-Jyan Wang, Tung-Hua Yeh
2007Identification of process/design issues during 0.18 µm technology qualification for space application.
Julie Ferrigno, Philippe Perdu, Kevin Sanchez, Dean Lewis
2007Impact of process variations on multicore performance symmetry.
Eric Humenay, David Tarjan, Kevin Skadron
2007Improve CAM power efficiency using decoupled match line scheme.
Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
2007Improving utilization of reconfigurable resources using two dimensional compaction.
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen
2007Incremental ABV for functional validation of TL-to-RTL design refinement.
Nicola Bombieri, Franco Fummi, Graziano Pravadelli
2007Industrial applications.
Xavier Olive, Jean-Marie Pasquet, Didier Flament
2007Instruction trace compression for rapid instruction cache simulation.
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel
2007Instruction-set customization for real-time embedded systems.
Huynh Phung Huynh, Tulika Mitra
2007Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB.
Ömer Yetik, Muharrem Orkun Saglamdemir, Selçuk Talay, Günhan Dündar
2007Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.
Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis
2007Interactive presentation: A middleware-centric design flow for networked embedded systems.
Franco Fummi, Giovanni Perbellini, R. Pietrangeli, Davide Quaglia
2007Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
2007Interactive presentation: A process splitting transformation for Kahn process networks.
Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock
2007Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver.
Mona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem
2007Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio.
Zhuan Ye, John Grosspietsch, Gokhan Memik
2007Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.
Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal
2007Interactive presentation: An FPGA implementation of decision tree classification.
Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
2007Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.
Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
2007Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm.
Esra Sahin, Ilker Hamzaoglu
2007Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.
Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
2007Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions.
Shireesh Verma, Ian G. Harris, Kiran Ramineni
2007Interactive presentation: Automatic hardware synthesis from specifications: a case study.
Roderick Bloem, Stefan J. Galler, Barbara Jobstmann, Nir Piterman, Amir Pnueli, Martin Weiglhofer
2007Interactive presentation: Automatic model generation for black box real-time systems.
Thomas Huining Feng, Lynn Wang, Wei Zheng, Sri Kanajan, Sanjit A. Seshia
2007Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.
Kunal P. Ganeshpure, Sandip Kundu
2007Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits.
Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
2007Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems.
Enrique Barajas, R. Cosculluela, D. Coutinho, Diego Mateo, José Luis González, I. Cairò, S. Banda, M. Ikeda
2007Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique.
Jerzy J. Dabrowski, Rashad Ramzan
2007Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.
Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto
2007Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2007Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model.
Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro
2007Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns.
Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner
2007Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search.
Sven van Haastregt, Peter M. W. Knijnenburg
2007Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.
Qiang Zhu, Aviral Shrivastava, Nikil D. Dutt
2007Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi
2007Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.
Christian Sauer, Matthias Gries, Sebastian Dirk
2007Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs.
Daniel Kroening, Natasha Sharygina
2007Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.
Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull
2007Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture.
Claudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma
2007Interactive presentation: Implementation of a transaction level assertion framework in SystemC.
Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull
2007Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
2007Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2007Interactive presentation: Low cost debug architecture using lossy compression for silicon debug.
Ehab Anis, Nicola Nicolici
2007Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor.
P. Yeung, A. Torres, P. Batra
2007Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations.
John Lataire, Gerd Vandersteen, Rik Pintelon
2007Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems.
Linwei Niu, Gang Quan
2007Interactive presentation: PowerQuest: trace driven data mining for power optimization.
Pietro Babighian, Gila Kamhi, Moshe Y. Vardi
2007Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy
2007Interactive presentation: Pulse propagation for the detection of small delay defects.
Michele Favalli, Cecilia Metra
2007Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics.
Philippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba
2007Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling.
Nishant R. Srivastava
2007Interactive presentation: Reliability-aware system synthesis.
Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich
2007Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's.
Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2007Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.
Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
2007Interactive presentation: Soft-core processor customization using the design of experiments paradigm.
David Sheldon, Frank Vahid, Stefano Lonardi
2007Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.
Yan Lin, Lei He
2007Interactive presentation: Statistical simulation of high-frequency bipolar circuits.
Wolfgang Schneider, Michael Schröter, W. Kraus, Holger Wittkopf
2007Interactive presentation: System level power optimization of Sigma-Delta modulator.
Fei Gong, Xiaobo Wu
2007Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs.
Siddharth Garg, Diana Marculescu
2007Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2007Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP.
Mario Schölzel
2007Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures.
Patrick Popp, Marco Di Natale, Paolo Giusto, Sri Kanajan, Claudio Pinello
2007Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices.
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
2007Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems.
Mehrdad Reshadi, Daniel Gajski
2007Introducing new verification methods into a company's design flow: an industrial user's point of view.
Robert Lissel, Joachim Gerlach
2007Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi
2007Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible?
Tohru Furuyama
2007Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law?
Alan Naumann
2007Layout-aware gate duplication and buffer insertion.
David Bañeres, Jordi Cortadella, Michael Kishinevsky
2007Life begins at 65: unless you are mixed signal?
Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, José E. da Franca, Christian Münker
2007Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks.
Felix Jesús Villanueva, David Villa, Francisco Moya, Jesús Barba, Fernando Rincón, Juan Carlos López
2007Low complexity LDPC code decoders for next generation standards.
Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci
2007Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system.
Marcus Schämann, Sebastian Hessel, Ulrich Langmann, Martin Bücker
2007Low-cost protection for SER upsets and silicon defects.
Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin
2007Low-g accelerometer fast prototyping for automotive applications.
Francesco D'Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, Alessandro Rocchi, Marco De Marinis
2007Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007Low-power warp processor for power efficient high-performance embedded systems.
Roman L. Lysecky
2007Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter.
C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet
2007Mapping multi-dimensional signals into hierarchical memory organizations.
Hongwei Zhu, Ilie I. Luican, Florin Balasa
2007Mapping the physical layer of radio standards to multiprocessor architectures.
Cyprian Grassmann, Mathias Richter, Mirko Sauermann
2007Maximum circuit activity estimation using pseudo-boolean satisfiability.
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007Memory bank aware dynamic loop scheduling.
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son, Ozcan Ozturk
2007Method for reducing jitter in multi-gigahertz ATE.
David C. Keezer, Dany Minier, Patrice Ducharme
2007Microarchitectural support for program code integrity monitoring in application-specific instruction set processors.
Yunsi Fei, Zhijie Jerry Shi
2007Microarchitecture floorplanning for sub-threshold leakage reduction.
Hushrav Mogal, Kia Bazargan
2007Microprocessors in the era of terascale integration.
Shekhar Borkar, Norman P. Jouppi, Per Stenström
2007Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns.
Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor
2007Minimum-energy LDPC decoder for real-time mobile application.
Weihuang Wang, Gwan Choi
2007Modeling and simulation alternatives for the design of networked embedded systems.
Elisa Alessio, Franco Fummi, Davide Quaglia, Maura Turolla
2007Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer.
Shuilong Huang, Huainan Ma, Zhihua Wang
2007New safety critical radio altimeter for airbus and related design flow.
David Hairion, S. Emeriau, E. Combot, Michel Sarlotte
2007Non-fractional parallelism in LDPC decoder implementations.
John Dielissen, Andries Hekstra
2007Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis.
Jonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain
2007On test generation by input cube avoidance.
Irith Pomeranz, Sudhakar M. Reddy
2007Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels.
Afxendios Tychopoulos, Odysseas G. Koufopavlou
2007Optimization-based wideband basis functions for efficient interconnect extraction.
Xin Hu, Tarek Moselhy, Jacob K. White, Luca Daniel
2007Optimized integration of test compression and sharing for SOC testing.
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
2007Optimizing instruction-set extensible processors under data bandwidth constraints.
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
2007Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware.
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo
2007Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis.
Simon Schliecker, Steffen Stein, Rolf Ernst
2007Performance analysis of multimedia applications using correlated streams.
Kai Huang, Lothar Thiele
2007Performance aware secure code partitioning.
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Richard R. Brooks
2007Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture.
Zahid Khan, Tughrul Arslan
2007Polynomial-time subgraph enumeration for automated instruction set extension.
Paolo Bonzini, Laura Pozzi
2007Portable multimedia SoC design: a global challenge.
Maurizio Paganini, Georg Kimmich, Stephane Ducrey, Guilhem Caubit, Vincent Coeffe
2007Power supply and power management in Ubicom.
2007Process variation tolerant low power DCT architecture.
Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy
2007QuteSAT: a robust circuit-based SAT solver for complex circuit structure.
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang
2007Random sampling of moment graph: a stochastic Krylov-reduction algorithm.
Zhenhai Zhu, Joel R. Phillips
2007Rapid and accurate latch characterization via direct Newton solution of setup/hold times.
Shweta Srivastava, Jaijeet S. Roychowdhury
2007Re-configuration of sub-blocks for effective application of time domain tests.
Jens Anders, Shaji Krishnan, Guido Gronthoud
2007Reconfigurable system-on-chip data processing units for space imaging instruments.
Björn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, Gang Zhou
2007Reduction of detected acceptable faults for yield improvement via error-tolerance.
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2007Register pointer architecture for efficient embedded processors.
Jongsoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
2007Remote testing and diagnosis of System-on-Chips using network management frameworks.
Oussama Laouamri, Chouki Aktouf
2007Resource prediction for media stream decoding.
Juan Hamers, Lieven Eeckhout
2007Reversible circuit technology mapping from non-reversible specifications.
Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur
2007Routing table minimization for irregular mesh NoCs.
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007Scalable reconfigurable channel decoder architecture for future wireless handsets.
Gummidipudi Krishnaiah, Nur Engin, Sergei Sawitzki
2007Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison.
Isabelle Puaut, Christophe Pais
2007Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support.
Laurent Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, El Mostapha Aboulhamid
2007Self-heating-aware optimal wire sizing under Elmore delay model.
Min Ni, Seda Ogrenci Memik
2007Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry.
Tejasvi Das, P. R. Mukund
2007Simulation platform for UHF RFID.
Vojtech Derbek, Christian Steger, Reinhold Weiss, Daniel Wischounig, Josef Preishuber-Pfluegl, Markus Pistauer
2007Simulation-based reusable posynomial models for MOS transistor parameters.
Varun Aggarwal, Una-May O'Reilly
2007Slow write driver faults in 65nm SRAM technology: analysis and March test solution.
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang
2007Soft error rate analysis for sequential circuits.
Natasa Miskov-Zivanov, Diana Marculescu
2007Speeding up SystemC simulation through process splitting.
Youssef N. Naguib, Rafik S. Guindi
2007Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application.
Amith Singhee, Rob A. Rutenbar
2007Statistical model order reduction for interconnect circuits considering spatial correlations.
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2007Stochastic modeling and optimization for robust power management in a partially observable system.
Qinru Qiu, Ying Tan, Qing Wu
2007Synthesis of task and message activation models in real-time distributed automotive systems.
Wei Zheng, Marco Di Natale, Claudio Pinello, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli
2007System level assessment of an optical NoC in an MPSoC platform.
Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor
2007System level clock tree synthesis for power optimization.
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt
2007Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture.
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner
2007Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL.
Hiren D. Patel, Sandeep K. Shukla
2007Task scheduling for reliable cache architectures of multiprocessor systems.
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2007Temperature and voltage aware timing analysis: application to voltage drops.
B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
2007Temperature aware task scheduling in MPSoCs.
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant
2007Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
2007Test cost reduction for SoC using a combined approach to test data compression and test scheduling.
Quming Zhou, Kedarnath J. Balakrishnan
2007Test quality analysis and improvement for an embedded asynchronous FIFO.
Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters
2007Testable design for advanced serial-link transceivers.
Mitchell Lin, Kwang-Ting (Tim) Cheng
2007Testing in the year 2020.
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
2007The ARTEMIS cross-domain architecture for embedded systems.
Hermann Kopetz
2007The impact of loop unrolling on controller delay in high level synthesis.
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda
2007The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space.
Thierry Pardessus, Heinrich Daembkes, Richard Arning
2007Thermally robust clocking schemes for 3D integrated circuits.
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
2007Timing simulation of interconnected AUTOSAR software-components.
Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel
2007Tool-support for the analysis of hybrid systems and models.
Andreas Bauer, Markus Pister, Michael Tautschnig
2007Toward a scalable test methodology for 2D-mesh Network-on-Chips.
Kim Petersén, Johnny Öberg
2007Towards total open source in aeronautics and space?
Peggy Aycinena, Eric Bantegnie, Gerard Ladier, Ralph Mueller, Franco Gasperoni, Alex Wilson
2007Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2007Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM.
Grégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier
2007Transient fault prediction based on anomalies in processor events.
Satish Narayanasamy, Ayse K. Coskun, Brad Calder
2007Two-level microprocessor-accelerator partitioning.
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid
2007Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.
Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks
2007Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.
Andreas Hansson, Martijn Coenen, Kees Goossens
2007Unknown blocking scheme for low control data volume and high observability.
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
2007Use of statistical timing analysis on real designs.
A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song
2007Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508.
Riccardo Mariani, Gabriele Boschi, Federico Colucci
2007Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system.
Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele
2007Using the inter- and intra-switch regularity in NoC switch testing.
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
2007Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
2007Verification-guided soft error resilience.
Sanjit A. Seshia, Wenchao Li, Subhasish Mitra
2007Very wide register: an asymmetric register file organization for low power embedded processors.
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
2007WAVSTAN: waveform based variational static timing analysis.
Saurabh K. Tiwary, Joel R. Phillips
2007What if you could design tomorrow's system today?
Neal Wingen
2007Working with process variation aware caches.
Madhu Mutyam, Narayanan Vijaykrishnan
2007Worst-case design and margin for embedded SRAM.
Robert C. Aitken, Sachin Idgunji
2007Yield-aware placement optimization.
Paolo Azzoni, Massimo Bertoletti, Nicola Dragone, Franco Fummi, Carlo Guardiani, W. Vendraminetto
2007pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate.
Tarek Moselhy, Xin Hu, Luca Daniel