DATE A

158 papers

YearTitle / Authors
2001A HW/SW partitioning algorithm for dynamically reconfigurable architectures.
Juanjo Noguera, Rosa M. Badia
2001A Skill-based library for retargetable embedded analog cores.
Jingnan Xu, João C. Vital, Nuno Horta
2001A boolean satisfiability-based incremental rerouting approach with application to FPGAs.
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2001A decade of reconfigurable computing: a visionary retrospective.
Reiner W. Hartenstein
2001A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters.
Friedel Gerfers, Yiannos Manoli
2001A framework for fast hardware-software co-simulation.
Andreas Hoffmann, Tim Kogel, Heinrich Meyr
2001A graph based algorithm for optimal buffer insertion under accurate delay models.
Youxin Gao, D. F. Wong
2001A hardware-software operating system for heterogeneous designs.
José Manuel Moya, Francisco Moya, Juan Carlos López
2001A methodology for interfacing open source systemC with a third party software.
Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois
2001A model for describing communication between aggregate objects in the specification and design of embedded systems.
Kjetil Svarstad, Gabriela Nicolescu, Ahmed Amine Jerraya
2001A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.
Oscar Garnica, Juan Lanchares, Román Hermida
2001A register-transfer-level fault simulator for permanent and transient faults in embedded processors.
C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus
2001A regularity-based hierarchical symbolic analysis method for large-scale analog networks.
Alex Doboli, Ranga Vemuri
2001A static power estimation methodolodgy for IP-based design.
Xun Liu, Marios C. Papaefthymiou
2001A universal communication model for an automotive system integration platform.
Thilo Demmeler, Paolo Giusto
2001AIL: description of a global electronic architecture at the vehicle scale.
Arjun Panday, Damien Couderc, Simon Marichalar
2001Abstraction of word-level linear arithmetic functions from bit-level component descriptions.
Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti
2001Access pattern based local memory customization for low power embedded systems.
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
2001Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
2001Allocation and scheduling of conditional task graph in hardware/software co-synthesis.
Yuan Xie, Wayne H. Wolf
2001An adaptive algorithm for low-power streaming multimedia processing.
Andrea Acquaviva, Luca Benini, Bruno Riccò
2001An efficient architecture model for systematic design of application-specific multiprocessor SoC.
Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2001An efficient learning procedure for multiple implication checks.
Yakov Novikov, Evguenii I. Goldberg
2001An improved hierarchical classification algorithm for structural analysis of integrated circuits.
Markus Olbrich, Achim Rein, Erich Barke
2001An integrated system-on-chip test framework.
Erik Larsson, Zebo Peng
2001An operation rearrangement technique for power optimization in VLIM instruction fetch.
Dongkun Shin, Jihong Kim, Naehyuck Chang
2001Analog design for reuse - case study: very low-voltage sigma-delta modulator.
Mohamed Dessouky, Andreas Kaiser, Marie-Minerve Louërat, Alain Greiner
2001Analog/mixed-signal IP modeling for design reuse.
Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
2001AnalogRouter: a new approach of current-driven routing for analog circuits.
Jens Lienig, Goeran Jerke, Thorsten Adler
2001Analysis of EME produced by a microcontroller operation.
Franco Fiori, Francesco Musolino
2001Annotated data types for addressed token passing networks.
Gordon Cichon, Winthir Brunnbauer
2001Architecture driven partitioning.
Joachim Küter, Erich Barke
2001Automatic datapath tile placement and routing.
Tatjana Serdar, Carl Sechen
2001Automatic generation and targeting of application specific operating systems and embedded systems software.
Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
2001Automatic nonlinear memory power modelling.
Eike Schmidt, Gerd Jochens, Lars Kruse, Frans Theeuwen, Wolfgang Nebel
2001Behavioral synthesis with systemC.
George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou
2001Biasing symbolic search by means of dynamic activity profiles.
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
2001Binary decision diagram with minimum expected path length.
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
2001C/C++: progress or deadlock in system-level specification.
Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
2001CAD for RF circuits.
Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
2001CMOS open defect detection by supply current test.
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2001CMOS sizing rule for high performance long interconnects.
Gregorio Cappuccino, Giuseppe Cocorullo
2001CPU for PlayStation 2.
Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto
2001Cache conscious data layout organization for embedded multimedia applications.
Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man
2001Circuit partitioning for efficient logic BIST synthesis.
Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich
2001Clustering based fast clock scheduling for light clock-tree.
Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
2001Code placement in hardware/software co-synthesis to improve performance and reduce cost.
Sri Parameswaran
2001Combinational equivalence checking using Boolean satisfiability and binary decision diagrams.
Sherief Reda, Ashraf Salem
2001Component selection and matching for IP-based design.
Ting Zhang, Luca Benini, Giovanni De Micheli
2001Constraint satisfaction for storage files with Fifos or stacks during scheduling.
Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
2001Crosstalk noise in future digital CMOS circuits.
Chr. Werner, Ralf Goettsche, A. Wörner, Ulrich Ramacher
2001Data management: limiter or accelerator for electronic design creativity.
Hans-Ulrich Heidbrink
2001Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
Irith Pomeranz, Sudhakar M. Reddy
2001Design challenges and emerging EDA solutions in mixed-signal IC design.
Georges G. E. Gielen
2001Design methodology for PicoRadio networks.
Julio Leao da Silva Jr., J. Shamberger, M. Josie Ammer, Chunlong Guo, Suet-Fei Li, Rahul C. Shah, Tim Tuan, Michael Sheets, Jan M. Rabaey, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli, Paul K. Wright
2001Design of low-power high-speed maximum a priori decoder architectures.
Alexander Worm, Holger Lamm, Norbert Wehn
2001Deterministic software-based self-testing of embedded processor cores.
Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
2001Diagnosis for scan-based BIST: reaching deep into the signatures.
Ismet Bayraktaroglu, Alex Orailoglu
2001Dual transitions petri net based modelling technique for embedded systems specification.
Mauricio Varea, Bashir M. Al-Hashimi
2001Efficient and passive modeling of transmission lines by using differential quadrature method.
Qinwei Xu, Pinaki Mazumder
2001Efficient bit-error-rate estimation of multicarrier transceivers.
Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens
2001Efficient finite field digital-serial multiplier architecture for cryptography applications.
Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto
2001Efficient inductance extraction via windowing.
Michael W. Beattie, Lawrence T. Pileggi
2001Efficient on-line testing method for a floating-point adder.
Alexander V. Drozd, M. V. Lobachev
2001Efficient spectral techniques for sequential ATPG.
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
2001Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.
Anshuman Chandra, Krishnendu Chakrabarty
2001Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model.
Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2001Electronic system design methodology: Europe's positioning.
Ahmed Amine Jerraya, Gérard Matheron
2001Embedded tutorial: TRP: integrating embedded test and ATE.
Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
2001Embedded tutorial: current trends in the design of automotive electronic systems.
Peter van Staa, Thomas Beck
2001Exact fault simulation for systems on Silicon that protects each core's intellectual property.
Md. Saffat Quasem, Sandeep K. Gupta
2001Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.
Qingjian Yu, Ernest S. Kuh
2001Exploiting data forwarding to reduce the power budget of VLIW embedded processors.
Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
2001Extending lifetime of portable systems by battery scheduling.
Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
2001From DFT to systems test - a model based cost optimization tool.
Michael G. Wahl, Anthony P. Ambler, Christoph Maaß, Mohammed Rahman
2001Full chip false timing path identification: applications to the PowerPCTM microprocessors.
Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
2001Functional test generation for behaviorally sequential models.
Fabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi
2001Functional units with conditional input/output behavior in VLIW processors.
Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá
2001Further improve circuit partitioning using GBAW logic perturbation techniques.
Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng
2001Generalized reasoning scheme for redundancy addition and removal logic optimization.
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
2001Generating production quality software development tools using a machine description language.
Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
2001Generation of minimal size code for scheduling graphs.
Claudio Passerone, Yosinori Watanabe, Luciano Lavagno
2001Generation of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities.
Bernhard Burdiek
2001HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
2001Heuristic datapath allocation for multiple wordlength systems.
George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2001Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.
Iyad Ouaiss, Ranga Vemuri
2001High quality behavioral verification using statistical stopping criteria.
Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
2001High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
2001High-quality sub-function construction in functional decomposition based on information relationship measures.
Lech Józwiak, Artur Chojnacki
2001Implementation of a linear histogram BIST for ADCs.
Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001Implementation of the ATI flipper chip.
Anand Mandapati
2001In-place delay constrained power optimization using functional symmetries.
Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska
2001Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints.
Alex Doboli
2001LPSAT: a unified approach to RTL satisfiability.
Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
2001Low complexity FIR filters using factorization of perturbed coefficients.
Cassondra Neau, Khurram Muhammad, Kaushik Roy
2001Low-power systems on chips (SOCs).
Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés
2001Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks.
Zhining Huang, Sharad Malik
2001Managing the SoC design challenge with "Soft" hardware.
Ron Wilson
2001Memory fault diagnosis by syndrome compression.
Jin-Fu Li, Cheng-Wen Wu
2001MetaRTL: raising the abstraction level of RTL design.
Jianwen Zhu
2001Methods and tools for systems engineering of automotive electronic architectures.
Jakob Axelsson
2001Microprocessor power analysis by labeled simulation.
Cheng-Ta Hsieh, Lung-sheng Chen, Massoud Pedram
2001Minimizing stand-by leakage power in static CMOS circuits.
Srinath R. Naidu, E. T. A. F. Jacobs
2001Minimizing the number of floating bias voltage sources with integer linear programming.
Erhan Yildiz, Arie van Staveren, Chris J. M. Verhoeven
2001Mixed-level cosimulation for fine gradual refinement of communication in SoC design.
Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya
2001Modeling crosstalk noise for deep submicron verification tools.
Pirouz Bazargan-Sabet, Fabrice Ilponse
2001Modeling electromagnetic emission of integrated circuits for system analysis.
P. Kralicek, Werner John, Heyno Garbe
2001Modelling SoC devices for virtual test using VHDL.
Marco Rona, Gunter Krampl
2001Network processors: a perspective on market requirements, processor architectures and embedded S/W tools.
Pierre G. Paulin, Faraydon Karim, Paul Bromley
2001On applying the set covering model to reseeding.
Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
2001On automatic analysis of geometrically proximate nets in VSLI layout.
Sandeep Koranne, Om Prakash Gangwal
2001On the impact of on-chip inductance on signal nets under the influence of power grid noise.
Tom Chen
2001On the test of microprocessor IP cores.
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2001On the verification of synthesized designs using automatically generated transformational witnesses.
Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
2001On-the-fly layout generation for PTL macrocells.
Luca Macchiarulo, Luca Benini, Enrico Macii
2001Optimal FPGA module placement with temporal precedence constraints.
Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2001Optimization of error detecting codes for the detection of crosstalk originated errors.
Michele Favalli, Cecilia Metra
2001Order determination for frequency compensation of negative-feedback systems.
Arie van Staveren, Chris J. M. Verhoeven
2001PRMDL: a machine description language for clustered VLIW architectures.
Andrei Sergeevich Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven
2001Performance improvement of multi-processor systems cosimulation based on SW analysis.
Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
2001Power aware microarchitecture resource scaling.
Anoop Iyer, Diana Marculescu
2001Power-efficient layered turbo decoder processor.
John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf
2001Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs.
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
2001Probabilistic application modeling for system-level perfromance analysis.
Radu Marculescu, Amit Nandi
2001Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001
Wolfgang Nebel, Ahmed Jerraya
2001Property-specific witness graph generation for guided simulation.
Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
2001Reliable estimation of execution time of embedded software.
Paolo Giusto, Grant Martin, Edwin A. Harcourt
2001Repeater block planning under simultaneous delay and transition time constraints.
Probir Sarkar, Cheng-Kok Koh
2001Retargeting of mixed-signal blocks for SoCs.
Rafael Castro-López, Francisco V. Fernández, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
2001SEU effect analysis in an open-source router via a distributed fault injection environment.
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2001SH-4 RISC microprocessor for multimedia, game machine.
Susumu Narita
2001Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
Irith Pomeranz, Sudhakar M. Reddy
2001Simulation method to extract characteristics for digital wireless communication systems.
Luong Nguyen, Vincent Janicot
2001Simulation-guided property checking based on a multi-valued AR-automata.
Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel
2001Slicing tree is a complete floorplan representation.
Minghorng Lai, D. F. Wong
2001Spectral decision diagrams using graph transformations.
Mitchell A. Thornton, Rolf Drechsler
2001Standard bus vs. bus wrapper: what is the best solution for future SoC integration?
C. Yeung, Anssi Haverinen, Graham Matthews, Jonathan Morris, Jauher Zaidi
2001Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.
Zaid Al-Ars, Ad J. van de Goor
2001Static memory allocation by pointer analysis and coloring.
Jianwen Zhu
2001Streaming BDD manipulation for large-scale combinatorial problems.
Shin-ichi Minato, Shinya Ishihara
2001Susceptibility of analog cells to substrate interference.
Franco Fiori
2001System safety through automatic high-level code transformations: an experimental evaluation.
Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001System-on-a-chip processor synchronization support in hardware.
Bilge Saglam Akgul, Vincent John Mooney III
2001SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design.
Robert Siegmund, Dietmar Müller
2001Task concurrency management methodology summary.
Chun Wong, Paul Marchal, Peng Yang, Francky Catthoor, Hugo De Man, Aggeliki S. Prayati, Nathalie Cossement, Rudy Lauwereins, Diederik Verkest
2001Test generation based diagnosis of device parameters for analog circuits.
Sasikumar Cherubal, Abhijit Chatterjee
2001Testability trade-offs for BIST RTL data paths: the case for three dimensional design space.
Nicola Nicolici, Bashir M. Al-Hashimi
2001Testing TAPed cores and wrapped cores with the same test access mechanism.
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
2001The programmable platform: does one size fit all?
A. Lock, Raul Camposano, Heinrich Meyr
2001The simulation semantics of systemC.
Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller
2001Timing simulation of digital circuits with binary decision diagrams.
Raimund Ubar, Artur Jutman, Zebo Peng
2001Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology.
Rocío del Río, Josep Lluís de la Rosa, Fernando Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
2001Towards a better understanding of failure modes and test requirements of ADCs.
Andreas Lechner, Andrew Richardson, B. Hermes
2001Two approaches for developing generic components in VHDL.
Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas
2001Using SAT for combinational equivalence checking.
Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
2001Using mission logic for embedded testing.
Rainer Dorsch, Hans-Joachim Wunderlich
2001Vehicle electric/electronic architecture - one of the most important challenges for OEM's.
G. Hettich, Thomas Thurner
2001dibSIM: a parallel functional logic simulator allowing dynamic load balancing.
Klaus Hering, Jork Löser, Jens Markwardt