| 2000 | 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France Ivo Bolsens |
| 2000 | A 50 Mbit/s Iterative Turbo-Decoder. Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni |
| 2000 | A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang |
| 2000 | A BIST Scheme for On-Chip ADC and DAC Testing. Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng |
| 2000 | A Bus Delay Reduction Technique Considering Crosstalk. Kei Hirose, Hiroto Yasuura |
| 2000 | A Design Automation Roadmap for Europe Panel discussion. Joseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer |
| 2000 | A Discrete-Time Battery Model for High-Level Power Estimation. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
| 2000 | A Fault Simulation Methodology for MEMS. Richard Rosing |
| 2000 | A Flexible Specification Framework for Hardware-Software Codesign. José Manuel Moya, Francisco Moya, Juan Carlos López, Santiago Domínguez |
| 2000 | A Generic Architecture for On-Chip Packet-Switched Interconnections. Pierre Guerrier, Alain Greiner |
| 2000 | A Hardware Platform for VLIW Based Emulation of Digital Designs. Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel |
| 2000 | A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits. Oscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez |
| 2000 | A Memory Architecture with 4-Address Configurations for Video Signal Processing. Sunho Chang, Jong-Sun Kim, Lee-Sup Kim |
| 2000 | A New Approach for Computation of Timing Jitter in Phase Locked Loops. Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney |
| 2000 | A New Effective And Efficient Multi-Level Partitioning Algorithm. Youssef Saab |
| 2000 | A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. Sungju Park, TaeHyung Kim |
| 2000 | A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level. Norbert Fröhlich, Volker Gloeckel, Josef Fleischmann |
| 2000 | A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. Tohru Ishihara, Hiroto Yasuura |
| 2000 | A Single Phase Latch for High Speed GaAs Domino Circuits. Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, Javier Sosa |
| 2000 | A System-Level Synthesis Algorithm with Guaranteed Solution Quality. U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary |
| 2000 | A VHDL Error Simulator for Functional Test Generation. Alessandro Fin, Franco Fummi |
| 2000 | A Versatile Built-In Self-Test Scheme for Delay Fault Testing. Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos |
| 2000 | A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas |
| 2000 | A Web-Based System for Assessing and Searching for Designs. Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker |
| 2000 | Abstraction from Counters: An Application on Real-Time Systems. George Logothetis, Klaus Schneider |
| 2000 | All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee |
| 2000 | Alternative Test Methods Using IEEE 1149.4. Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik |
| 2000 | An Efficient Heuristic Approach to Solve the Unate Covering Problem. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo |
| 2000 | An Experimental Study of Satisfiability Search Heuristics. Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva |
| 2000 | An Incremental Specification Flow for Real Time Embedded Systems. Alex Niemegeers, Gjalt G. de Jong |
| 2000 | An Integrated Design Environment for Early Stage Conceptual Design. Jingyan Zuo, Stephen W. Director |
| 2000 | An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. Satish Ganesan, Ranga Vemuri |
| 2000 | An Object Oriented Design Method for Reconfigurable Computing Systems. Martyn Edwards, Peter Green |
| 2000 | An on Chip ADC Test Structure. Yun-Che Wen, Kuen-Jong Lee |
| 2000 | Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. Makoto Sugihara, Hiroto Yasuura, Hiroshi Date |
| 2000 | Analysis of High-Level Address Code Transformations for Programmable Processors. Sumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor |
| 2000 | Analyzing Real-Time Systems. Jürgen Ruf, Thomas Kropf |
| 2000 | Architectural Power Optimization by Bus Splitting. Cheng-Ta Hsieh, Massoud Pedram |
| 2000 | Architecture Exploration of Parameterizable EPIC SOC Architectures. Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
| 2000 | Area Optimization of Analog Circuits Considering Matching Constraints. Christian Paulus, Ulrich Kleine, Roland Thewes |
| 2000 | Assessing the Cost Effectiveness of Integrated Passives. Michael Scheffler, Gerhard Tröster |
| 2000 | Automatic Abstraction for Worst-Case Analysis of Discrete Systems. Felice Balarin |
| 2000 | Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. Jens Schönherr, Bernd Straube |
| 2000 | Automatic Lighthouse Generation for Directed State Space Search. Praveen Yalagandula, Adnan Aziz, Vigyan Singhal |
| 2000 | Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti |
| 2000 | Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch |
| 2000 | Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis. Paul Pop, Petru Eles, Zebo Peng |
| 2000 | CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki |
| 2000 | Clocktree RLC Extraction with Efficient Inductance Modeling. Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He |
| 2000 | Code Selection for Media Processors with SIMD Instructions. Rainer Leupers |
| 2000 | Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens |
| 2000 | Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors. Axel Jantsch, Per Bjuréus |
| 2000 | Constraint-Driven System Partitioning. Marisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López |
| 2000 | Constructive Library-Aware Synthesis Using Symmetries. Victor N. Kravets, Karem A. Sakallah |
| 2000 | Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. Lorena Anghel, Michael Nicolaidis |
| 2000 | Cost and Benefit Models for Logic and Memory BIST. Juin-Ming Lu, Cheng-Wen Wu |
| 2000 | Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. Adam Morawiec, Raimund Ubar, Jaan Raik |
| 2000 | Cycle-True Simulation of the ST10 Microcontroller. Lovic Gauthier, Ahmed Amine Jerraya |
| 2000 | Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. Jovanka Ciric, Gin Yee, Carl Sechen |
| 2000 | Delay-Insensitive Interface Specification and Synthesis. Mark B. Josephs, Dennis P. Furey |
| 2000 | Design and Test Space Exploration of Transport-Triggered Architectures. V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
| 2000 | Designing Closer to the Edge. Sani R. Nassif |
| 2000 | Detecting Undetectable Controller Faults Using Power Analysis. Joan Carletta, Christos A. Papachristou, Mehrdad Nourani |
| 2000 | Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched Filter. Dirk Weiler, Olaf Machul, Dirk Hammerschmidt, Bedrich J. Hosticka |
| 2000 | Diagnostic Testing of Embedded Memories Using BIST. Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick |
| 2000 | Dynamic Power Management of Laptop Hard Disk. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli |
| 2000 | Effective Low Power BIST for Datapaths. Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
| 2000 | Efficient Power Co-Estimation Techniques for System-on-Chip Design. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
| 2000 | Efficient Resource Arbitration in Reconfigurable Computing Environments. Iyad Ouaiss, Ranga Vemuri |
| 2000 | Evaluating System Dependability in a Co-Design Framework. Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno |
| 2000 | Evaluation of Interconnects with TDR. Ulf Pillkahn |
| 2000 | Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits. Dirk W. Hoffmann, Thomas Kropf |
| 2000 | Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. Jörg Henkel, Tony Givargis, Frank Vahid |
| 2000 | Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. Xiaoping Tang, D. F. Wong, Ruiqi Tian |
| 2000 | Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi |
| 2000 | Faster Optimal Single-Row Placement with Fixed Ordering. Ulrich Brenner, Jens Vygen |
| 2000 | Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications. Frederik Vermeulen, Francky Catthoor, Hugo De Man, Diederik Verkest |
| 2000 | Free MDD-Based Software Optimization Techniques for Embedded Systems. Chunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 2000 | From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time Systems. Carsten Rust, Friedhelm Stappert, Peter Altenbernd, Jürgen Tacken |
| 2000 | Functional Test Generation for Full Scan Circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Gate Sizing Using a Statistical Delay Model. E. T. A. F. Jacobs, Michel R. C. M. Berkelaar |
| 2000 | HW/SW Codesign of an Engine Management System. Massimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Claudio Turchetti |
| 2000 | How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis |
| 2000 | Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check. Valery A. Vardanian, Liana B. Mirzoyan |
| 2000 | Improving the Schedule Quality of Static-List Time-Constrained Scheduling. Sriram Govindarajan, Ranga Vemuri |
| 2000 | Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs. Carsten Wegener, Michael Peter Kennedy |
| 2000 | Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. Juan M. Díez, Juan Carlos López |
| 2000 | Iterative Abstraction-Based CTL Model Checking. Jae-Young Jang, In-Ho Moon, Gary D. Hachtel |
| 2000 | Layout Compaction for Yield Optimization via Critical Area Minimization. Youcef Bourai, Chuanjin Richard Shi |
| 2000 | Layout-Oriented Synthesis of High Performance Analog Circuits. Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte |
| 2000 | Logic Simulation Using Networks of State Machines. Peter M. Maurer |
| 2000 | Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel |
| 2000 | MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. Per Bjuréus, Axel Jantsch |
| 2000 | Meeting Delay Constraints in DSM by Minimal Repeater Insertion. I-Min Liu, Adnan Aziz, D. F. Wong |
| 2000 | Memory Arbitration and Cache Management in Stream-Based Systems. Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen |
| 2000 | Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. José Machado da Silva, J. Soeiro Duarte, José Silva Matos |
| 2000 | Multi-Node Static Logic Implications for Redundancy Identification. Kabir Gulrajani, Michael S. Hsiao |
| 2000 | Non-Linear Components for Mixed Circuits Analog Front-End. Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco |
| 2000 | On Applying Incremental Satisfiability to Delay Fault Testing. Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva |
| 2000 | On Using Satisfiability-Based Pruning Techniques in Covering Algorithms. Vasco M. Manquinho, João Marques-Silva |
| 2000 | On the Generation of Multiplexer Circuits for Pass Transistor Logic. Christoph Scholl, Bernd Becker |
| 2000 | On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. Cecilia Metra, Michele Favalli, Bruno Riccò |
| 2000 | Optimal Hardware Pattern Generation for Functional BIST. Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich |
| 2000 | Parallel and Distributed VHDL Simulation. Dragos Lungeanu, Chuanjin Richard Shi |
| 2000 | Parametric Fault Simulation and Test Vector Generation. Khaled Saab, Naim Ben-Hamida, Bozena Kaminska |
| 2000 | Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. Balakrishna Kumthekar, Fabio Somenzi |
| 2000 | Predicting Coupled Noise in RC Circuits. Bernard N. Sheehan |
| 2000 | Protocol Stack-Based Telecom-Emulator. Takahiro Murooka, Toshiaki Miyazaki |
| 2000 | Quantitative Comparison of Power Management Algorithms. Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini |
| 2000 | Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. José T. de Sousa, Vishwani D. Agrawal |
| 2000 | Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C. Luc Séméria, Koichi Sato, Giovanni De Micheli |
| 2000 | Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. Stefan Pees, Andreas Hoffmann, Heinrich Meyr |
| 2000 | Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski |
| 2000 | Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. Nicola Nicolici, Bashir M. Al-Hashimi |
| 2000 | Shared Memory Implementations of Synchronous Dataflow Specifications. Praveen K. Murthy, Shuvra S. Bhattacharyya |
| 2000 | Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. Thorsten Adler, Erich Barke |
| 2000 | Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing. Uberto Girola, Agostino Picciriello, David Vincenzoni |
| 2000 | Standards for System-Level Design: Practical Reality or Solution in Search of a Question? Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee |
| 2000 | Static Timing Analysis Taking Crosstalk into Account. Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
| 2000 | Static Timing Analysis of Embedded Software on Advanced Processor Architectures. André Hergenhan, Wolfgang Rosenstiel |
| 2000 | Stay Away from Minimum Design-Rule Values. Chris W. H. Strolenberg |
| 2000 | Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits. Alper Demir, Peter Feldmann |
| 2000 | Structural Testing on Real Boards. Peter Bach, Michael Bosch |
| 2000 | Synthesis for Mixed CMOS/PTl Logic. Congguang Yang, Maciej J. Ciesielski |
| 2000 | System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi |
| 2000 | System Level Design Using C++. Diederik Verkest, Joachim Kunkel, Frank Schirrmeister |
| 2000 | System Level Online Power Management Algorithms. Dinesh Ramanathan, Rajesh K. Gupta |
| 2000 | System Synthesis for Multiprocessor Embedded Applications. Luigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada |
| 2000 | TOP: An Algorithm for Three-Level Optimization of PLDs. Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio |
| 2000 | Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn |
| 2000 | Techniques for Reducing Read Latency of Core Bus Wrappers. Roman L. Lysecky, Frank Vahid, Tony Givargis |
| 2000 | Technology Mapping and Retargeting for Field-Programmable Analog Arrays. Sree Ganesan, Ranga Vemuri |
| 2000 | Test Quality and Fault Risk in Digital Filter Datapath BIST. Laurence Goodby, Alex Orailoglu |
| 2000 | Test Synthesis for Mixed-Signal SOC Paths. Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu |
| 2000 | Testing Arithmetic Coprocessor in System Environment. Janusz Sosnowski, Tomasz Bech |
| 2000 | The Future of Flexible HW Platform Architectures Panel Discussion. Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers |
| 2000 | The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich |
| 2000 | The Road to Better Reliability and Yield Embedded DfM Tools. Kees Veelenturf |
| 2000 | Transformational Placement and Synthesis. Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty |
| 2000 | Tutorial Statement. Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf |
| 2000 | Virtual Fault Simulation of Distributed IP-Based Designs. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli |
| 2000 | Wave Steered FSMs. Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska |
| 2000 | Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. Youxin Gao, D. F. Wong |
| 2000 | XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool. F. M. Pérez-Montes, Fernando Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez |
| 2000 | Yield Improvement and Repair Trade-Off for Large Embedded Memories. Yervant Zorian |