| 1996 | A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs. Christian Legl, Bernd Wurth, Klaus Eckl |
| 1996 | A Description Language for Design Process Management. Peter R. Sutton, Stephen W. Director |
| 1996 | A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. Hiroyuki Higuchi, Yusuke Matsunaga |
| 1996 | A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi |
| 1996 | A Methodology for Concurrent Fabrication Process/Cell Library Optimization. Arun N. Lokanathan, Jay B. Brockman, John E. Renaud |
| 1996 | A New Complete Diagnosis Patterns for Wiring Interconnects. Sungju Park |
| 1996 | A New Hybrid Methodology for Power Estimation. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska |
| 1996 | A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis. Narayan R. Aluru, V. B. Nadkarni, James White |
| 1996 | A Probability-Based Approach to VLSI Circuit Partitioning. Shantanu Dutt, Wenyong Deng |
| 1996 | A Register File and Scheduling Model for Application Specific Processor Synthesis. Ehat Ercanli, Christos A. Papachristou |
| 1996 | A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. Chih-Ang Chen, Sandeep K. Gupta |
| 1996 | A Scalable Formal Verification Methodology for Pipelined Microprocessors. Jeremy R. Levitt, Kunle Olukotun |
| 1996 | A Sparse Image Method for BEM Capacitance Extraction. Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi |
| 1996 | A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits. Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma |
| 1996 | A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures. Steven Vercauteren, Bill Lin, Hugo De Man |
| 1996 | A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications. Bill Lin |
| 1996 | A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. Madhav P. Desai, Yao-Tsung Yen |
| 1996 | A Technique for Synthesizing Distributed Burst-mode Circuits. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson |
| 1996 | Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures. Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya |
| 1996 | An Bülent Basaran, Rob A. Rutenbar |
| 1996 | An AWE Technique for Fast Printed Circuit Board Delays. Bernard N. Sheehan |
| 1996 | An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. Christos A. Papachristou, Mark Spining, Mehrdad Nourani |
| 1996 | An Efficient Equivalence Checker for Combinational Circuits. Yusuke Matsunaga |
| 1996 | An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing. De-Sheng Chen, Majid Sarrafzadeh |
| 1996 | An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi |
| 1996 | Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems. Rajesh K. Gupta |
| 1996 | Analysis of RC Interconnections Under Ramp Input. Andrew B. Kahng, Sudhakar Muddu |
| 1996 | Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process. Eric W. Johnson, Luis A. Castillo, Jay B. Brockman |
| 1996 | Architectural Retiming: Pipelining Latency-Constrained Circuts. Soha Hassoun, Carl Ebeling |
| 1996 | Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng |
| 1996 | Behavioral Synthesis. Raul Camposano |
| 1996 | Bit-Level Analysis of an SRT Divider Circuit. Randal E. Bryant |
| 1996 | Characterization and Parameterized Random Generation of Digital Circuits. Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil |
| 1996 | Code Generation and Analysis for the Functional Verification of Microprocessors. Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas |
| 1996 | Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens |
| 1996 | Compact Vector Generation for Accurate Power Simulation. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee |
| 1996 | Compiled HW/SW Co-Simulation. Vojin Zivojnovic, Heinrich Meyr |
| 1996 | Computing Parametric Yield Adaptively Using Local Linear Models. Mien Li, Linda S. Milor |
| 1996 | Concurrent Analysis Techniques for Data Path Timing Optimization. Chuck Monahan, Forrest Brewer |
| 1996 | Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. Steven Vercauteren, Bill Lin, Hugo De Man |
| 1996 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming. Jaewon Oh, Iksoo Pyo, Massoud Pedram |
| 1996 | Delay Minimal Decomposition of Multiplexers in Technology Mapping. Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy |
| 1996 | Desensitization for Power Reduction in Sequential Circuits. Xiangfeng Chen, Peichen Pan, C. L. Liu |
| 1996 | Design Considerations and Tools for Low-voltage Digital System Design. Anantha P. Chandrakasan, Isabel Y. Yang, Carlin Vieri, Dimitri A. Antoniadis |
| 1996 | Design Methodologies for consumer-use video signal processing LSIs. Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa |
| 1996 | Design Methodology for Analog High Frequency ICs. Yasunori Miyahara, Yoshimoto Oumi, Seijiro Moriyama |
| 1996 | Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita |
| 1996 | Early Power Exploration - A World Wide Web Application. David Lidsky, Jan M. Rabaey |
| 1996 | Efficient AC and Noise Analysis of Two-Tone RF Circuits. Ricardo Telichevesky, Kenneth S. Kundert, Jacob White |
| 1996 | Efficient Approximation Algorithms for Floorplan Area Minimization. Danny Z. Chen, Xiaobo Hu |
| 1996 | Efficient Communication in a Design Environment. Idalina Videira, Paulo Veríssimo, Helena Sarmento |
| 1996 | Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms. Joel R. Philips, Eli Chiprout, David D. Ling |
| 1996 | Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems. Eric Verlind, Gjalt G. de Jong, Bill Lin |
| 1996 | Efficient Software Performance Estimation Methods for Hardware/Software Codesign. Kei Suzuki, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Electromigration Reliability Enhancement via Bus Activity Distribution. Aurobindo Dasgupta, Ramesh Karri |
| 1996 | Energy Characterization based on Clustering. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin |
| 1996 | Engineering Change in a Non-Deterministic FSM Setting. Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Enhanced Network Flow Algorithm for Yield Optimization. Cyrus Bamji, Enrico Malavasi |
| 1996 | Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. Carsten Borchers, Lars Hedrich, Erich Barke |
| 1996 | Error Correction Based on Verification Techniques. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1996 | Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. Michael Theobald, Steven M. Nowick, Tao Wu |
| 1996 | Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. Stephen Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic |
| 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. P. J. H. Elias, N. P. van der Meijs |
| 1996 | FADIC: Architectural Synthesis applied in IC Design. Jos A. Huisken, F. Welten |
| 1996 | Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance. Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II |
| 1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. Chung-Ping Chen, Yao-Wen Chang, D. F. Wong |
| 1996 | Formal Verification of Embedded Systems based on CFSM Networks. Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. Manish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant |
| 1996 | Functional Verification Methodology for the PowerPC 604 Microprocessor. James Monaco, David Holloway, Rajesh Raina |
| 1996 | Functional Verification Methodology of Chameleon Processor. Françoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet |
| 1996 | Glitch Analysis and Reduction in Register Transfer Level. Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | HDL Optimization Using Timed Decision Tables. Jian Li, Rajesh K. Gupta |
| 1996 | HEAT: Hierarchical Energy Analysis Tool. Janardhan H. Satyanarayana, Keshab K. Parhi |
| 1996 | Hardware Emulation for Functional Verification of K5. Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang, Jim Nishimura |
| 1996 | Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang |
| 1996 | High Performance BDD Package By Exploiting Memory Hiercharchy. Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | High-Level Synthesis for Testability: A Survey and Perspective. Kenneth D. Wagner, Sujit Dey |
| 1996 | Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits. Jaijeet S. Roychowdhury, Robert C. Melville |
| 1996 | Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. Aurobindo Dasgupta, Ramesh Karri |
| 1996 | How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together. Robert C. Hutchins, Shankar Hemmady |
| 1996 | I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor. Michael Kantrowitz, Lisa M. Noack |
| 1996 | Identifying Sequential Redundancies Without Search. Mahesh A. Iyer, David E. Long, Miron Abramovici |
| 1996 | Implementation of an Efficient Parallel BDD Package. Tony Stornetta, Forrest Brewer |
| 1996 | Improved Tool and Data Selection in Task Management. John W. Hagerman, Stephen W. Director |
| 1996 | Improving the Efficiency of Power Simulators by Input Vector Compaction. Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram |
| 1996 | Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor. Val Popescu, Bill McNamara |
| 1996 | Integrating Formal Verification Methods with A Conventional Project Design Flow. Ásgeir Th. Eiríksson |
| 1996 | Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. Balakrishnan Iyer, Ramesh Karri |
| 1996 | Issues and Answers in CAD Tool Interoperability. Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trivedi, Bill McCaffrey, Ted Vucurevich |
| 1996 | Layout Driven Selecting and Chaining of Partial Scan. Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang |
| 1996 | Lower Bounds on Test Resources for Scheduled Data Flow Graphs. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1996 | Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev |
| 1996 | Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. V. Chandramouli, Karem A. Sakallah |
| 1996 | Module Compaction in FPGA-based Regular Datapaths. Andreas Koch |
| 1996 | Multilevel Logic Synthesis for Arithmetic Functions. Chien-Chung Tsai, Malgorzata Marek-Sadowska |
| 1996 | Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios. Johannes Tausch, Jacob K. White |
| 1996 | Network Partitioning into Tree Hierarchies. Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng |
| 1996 | New Algorithms for Gate Sizing: A Comparative Study. Olivier Coudert, Ramsey W. Haddad, Srilatha Manne |
| 1996 | New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho |
| 1996 | New Spectral Linear Placement and Clustering Approach. Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng |
| 1996 | On Solving Covering Problems. Olivier Coudert |
| 1996 | On Static Compaction of Test Sequences for Synchronous Sequential Circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | Opportunities and Obstacles in Low-Power System-Level CAD. Andrew Wolfe |
| 1996 | Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. Peichen Pan, C. L. Liu |
| 1996 | Optimal Clock Skew Scheduling Tolerant to Process Variations. José Luis Neves, Eby G. Friedman |
| 1996 | Optimal Wire-Sizing Formular Under the Elmore Delay Model. Chung-Ping Chen, Yao-Ping Chen, D. F. Wong |
| 1996 | Optimized Code Generation of Multiplication-free Linear Transforms. Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar |
| 1996 | Optimizing Systems for Effective Block-Processing: The Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak |
| 1996 | Oscillation Control in Logic Simulation using Dynamic Dominance Grahps. Peter Dahlgren |
| 1996 | POSE: Power Optimization and Synthesis Environment. Sasan Iman, Massoud Pedram |
| 1996 | Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter. Mattan Kamon, Steve S. Majors |
| 1996 | Partial Scan Design Based on Circuit State Information. Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel |
| 1996 | Partitioning of VLSI Circuits and Systems. Frank M. Johannes |
| 1996 | Post-Layout Optimization for Deep Submicron Design. Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda |
| 1996 | Power Estimation of Cell-Based CMOS Circuits. Alessandro Bogliolo, Luca Benini, Bruno Riccò |
| 1996 | Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach. Mani B. Srivastava, Miodrag Potkonjak |
| 1996 | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. Thomas Pennino, Ellen J. Yoffa |
| 1996 | Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. Laurence Goodby, Alex Orailoglu |
| 1996 | RC-Interconnect Macromodels for Timing Simulation. Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi |
| 1996 | RTL Emulation: The Next Leap in System Verification. Sanjay Sawant, Paul Giordano |
| 1996 | Reducing Power Dissipation after Technology Mapping by Structural Transformations. Bernhard Rohfleisch, Alfred Kölbl, Bernd Wurth |
| 1996 | RuleBase: An Industry-Oriented Formal Verification Tool. Ilan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver |
| 1996 | Scheduling Techniques to Enable Power Management. José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar |
| 1996 | Serial Fault Emulation. Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape |
| 1996 | Sizing of Clock Distribution Networks for High Performance CPU Chips. Madhav P. Desai, Radenko Cvijetic, James Jensen |
| 1996 | Software Development in a Hardware Simulation Environment. Benny Schnaider, Einat Yogev |
| 1996 | Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations. Kevin J. Kerns, Andrew T. Yang |
| 1996 | State Reduction Using Reversible Rules. C. Norris Ip, David L. Dill |
| 1996 | Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation. Diana Marculescu, Radu Marculescu, Massoud Pedram |
| 1996 | Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. Jason Cong, Yean-Yow Hwang |
| 1996 | Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto |
| 1996 | Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems. Antonio R. W. Todesco, Teresa H.-Y. Meng |
| 1996 | Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen |
| 1996 | Synthesis by Spectral Translation Using Boolean Decision Diagrams. Jeffery P. Hansen, Masatoshi Sekine |
| 1996 | Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick |
| 1996 | Techniques for Verifying Superscalar Microprocessors. Jerry R. Burch |
| 1996 | Test Point Insertion: Scan Paths through Combinational Logic. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee |
| 1996 | The Automatic Generation of Functional Test Vectors for Rambus Designs. K. D. Jones, J. P. Privitera |
| 1996 | The Design of Mixed Hardware/Software Systems. Jay K. Adams, Donald E. Thomas |
| 1996 | Tutorial: Design of a Logic Synthesis System. Richard L. Rudell |
| 1996 | Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design. Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Useful-Skew Clock Routing With Gate Sizing for Low Power Design. Joe G. Xi, Wayne Wei-Ming Dai |
| 1996 | Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. Arjan J. van Genderen, N. P. van der Meijs |
| 1996 | Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. Guido Araujo, Sharad Malik, Mike Tien-Chien Lee |
| 1996 | VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems. Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser |
| 1996 | VDHL Development System and Coding Standard. Hans Sahm, Claus Mayer, Jörg Pleickhardt, Johannes Schuck, Stefan Späth |
| 1996 | VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. Douglas J. Smith |
| 1996 | VLSI Design and System Level Verification for the Mini-Disc. Tetsuya Fujimoto, Takashi Kambe |
| 1996 | Verification of Electronic Systems. Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha |
| 1996 | Verification of asynchronous circuits using Time Petri Net unfolding. Alexei L. Semenov, Alexandre Yakovlev |
| 1996 | Word Level Model Checking - Avoiding the Pentium FDIV Error. Edmund M. Clarke, Manpreet Khaira, Xudong Zhao |
| 1996 | iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang |