DAC A*

136 papers

YearTitle / Authors
1994A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules.
Gjalt G. de Jong, Bill Lin
1994A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.
Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski
1994A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs.
Thang Nguyen Bui, Byung Ro Moon
1994A Fully Implicit Algorithm for Exact State Minimization.
Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994A Gate-Delay Model for high-Speed CMOS Circuits.
Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
1994A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's.
Ikuo Harada, Hitoshi Kitazawa
1994A Methodology and Algorithms for Post-Placement Delay Optimization.
Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang
1994A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
José Monteiro, Srinivas Devadas, Bill Lin
1994A Modular Partitioning Approach for Asynchronous Circuit Synthesis.
Ruchir Puri, Jun Gu
1994A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections.
Monjurul Haque, Ali El-Zein, Salim Chowdhury
1994A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes.
S. C. Prasad, P. Anirudhan, Patrick W. Bosshart
1994A Time Abstraction Method for Efficient Verification of Communicating Systems.
Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man
1994A Unified Approach to Multilayer Over-the-Cell Routing.
Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
1994ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.
Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
1994Acyclic Multi-Way Partitioning of Boolean Networks.
Jason Cong, Zheng Li, Rajive L. Bagrodia
1994Algorithmic Aspects of Three Dimensional MCM Routing.
Qiong Yu, Sandeep Badida, Naveed A. Sherwani
1994An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data.
Luís Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert
1994An Efficient Path Delay Fault Coverage Estimator.
Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
1994An Efficient Zero-Skew Routing Algorithm.
Masato Edahiro
1994An Exact Algorithm for Selecting Partial Scan Flip-Flops.
Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
1994Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.
Ramesh Karri, Alex Orailoglu
1994Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs.
Anurag P. Gupta, Daniel P. Siewiorek
1994Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals.
Hong Shin Jun, Sun Young Hwang
1994Automatic Verification of Pipelined Microprocessors.
Vishal Bhagwati, Srinivas Devadas
1994Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths.
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
1994BDD Variable Ordering for Interacting Finite State Machines.
Adnan Aziz, Serdar Tasiran, Robert K. Brayton
1994Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1.
Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno
1994Basic Gate Implementation of Speed-Independent Circuits.
Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev
1994Boolean Matching Using Generalized Reed-Muller Forms.
Chien-Chung Tsai, Malgorzata Marek-Sadowska
1994Boolean Matching of Sequential Elements.
Shankar Krishnamoorthy, Frédéric Mailhot
1994Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs.
Shin-ichi Minato
1994Chain Closure: A Problem in Molecular CAD.
Maria Domenica Di Benedetto, Pasquale Lucibello, Alberto L. Sangiovanni-Vincentelli, Ken Yamaguchi
1994Circuit Partitioning for Huge Logic Emulation Systems.
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1994Clock Grouping: A Low Cost DFT Methodology for Delay Testing.
Wen-Chang Fang, Sandeep K. Gupta
1994Clock Period Optimization During Resource Sharing and Assignment.
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994Clock Skew Minimization During FPGA Placement.
Kai Zhu, D. F. Wong
1994Cost of Silicon Viewed from VLSI Design Perspective.
Wojciech Maly
1994DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel).
Patrick C. McGeer, Steven Trimberger, Erik Carlson, Dave Hightower, Ulrich Lauther, Alberto L. Sangiovanni-Vincentelli
1994DFBT: A Design-for-Testability Method Based on Balance Testing.
Krishnendu Chakrabarty, John P. Hayes
1994Data Flow Partitioning for Clock Period and Latency Minimization.
Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng
1994Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model.
Andrew B. Kahng, Sudhakar Muddu
1994Design Automation Tools for FPGA Design (Panel).
Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier
1994Design Methodology Management Using Graph Grammars.
Reid A. Baldwin, Moon-Jung Chung
1994Design Reuse: Fact or Fiction? (Panel).
Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura
1994Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
Irith Pomeranz, Sudhakar M. Reddy
1994Dynamic Search-Space Pruning Techniques in Path Sensitization.
João P. Marques Silva, Karem A. Sakallah
1994Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
1994Efficient Simulation of Lossy and Dispersive Transmission Lines.
Tuyen V. Nguyen
1994Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching.
Miodrag Potkonjak, Mani B. Srivastava, Anantha P. Chandrakasan
1994Error Diagnosis for Transistor-Level Verification.
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin
1994Exact Minimum Cycle Times for Finite State Machines.
William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1994Executive Perspective and Vision of the Future of EDA (Panel).
Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett
1994Experience with Image Compression Chip Design using Unified System Construction Tools.
Pravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batista, Alice C. Parker
1994Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.
Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
1994Fitting Formal Methods into the Design Cycle.
Kenneth L. McMillan
1994Formally Verifying a Microprocessor Using a Simulation Methodology.
Derek L. Beatty, Randal E. Bryant
1994Functional Test Generation for FSMs by Fault Extraction.
Bapiraju Vinnakota, Jason Andrews
1994Generation of High Quality Non-Robust Tests for Path Delay Faults.
Kwang-Ting Cheng, Hsi-Chuan Chen
1994Global Scheduling for High-Level Synthesis Applications.
Yaw Fann, Minjoong Rim, Rajiv Jain
1994HSIS: A BDD-Based Environment for Formal Verification.
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994Hardware-Software Co-Design and ESDA.
Kurt Keutzer
1994Hardware/Software Co-Simulation.
James A. Rowson
1994Heuristic Minimization of BDDs Using Don't Cares.
Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1994Hitachi-PA/50, SH Series Microcontroller.
Tadahiko Nishimukai
1994Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.
Pranav Ashar, Sharad Malik
1994Improving the Accuracy of Circuit Activity Measurement.
Bhanu Kapoor
1994Incorporating Speculative Execution in Exact Control-Dependent Scheduling.
Ivan P. Radivojevic, Forrest Brewer
1994Intellectual Property Protection in the EDA Industry.
Dennis S. Fernandez
1994Interface Timing Verification with Application to Synthesis.
Elizabeth A. Walkup, Gaetano Borriello
1994Layout Driven Logic Synthesis for FPGAs.
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
1994Lessons in Language Design: Cost/Benefit analysis of VHDL Features.
Oz Levia, Serge Maginot, Jacques Rouillard
1994Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation.
Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass
1994Low Power CMOS Design Strategies.
Matthias Schöbinger, Tobias G. Noll
1994MIST - A Design Aid for Programmable Pipelined Processors.
Albert E. Casavant
1994MONSTR: A Complete Thermal Simulator of Electronic Systems.
Vladimir A. Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director
1994Management Issues in Eda.
Ajit M. Prabhu
1994Manifestations of Heterogeneity in Hardware/Software Co-Design.
Asawaree Kalavade, Edward A. Lee
1994Memory Estimation for High Level Synthesis.
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabaey
1994Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.
Ian G. Harris, Alex Orailoglu
1994Microprocessor Testing: Which Technique is Best? (Panel).
Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1994Minimal Delay Interconnect Design Using Alphabetic Trees.
Ashok Vittal, Malgorzata Marek-Sadowska
1994Minimization of Memory Traffic in High-Level Synthesis.
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt
1994Modeling of Intermediate Node States in switch-Level Networks.
Peter Dahlgren, Peter Lidén
1994Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming.
Charles J. Alpert, Andrew B. Kahng
1994Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect.
Roman Kuznar, Franc Brglez, Baldomir Zajc
1994New Techniques for Efficient Verification with Implicitly Conjoined BDDs.
Alan J. Hu, Gary York, David L. Dill
1994OTTER: Optimal Termination of Transmission Lines Excluding Radiation.
Rohini Gupta, Lawrence T. Pillage
1994On Improving Fault Diagnosis for Synchronous Sequential Circuits.
Irith Pomeranz, Sudhakar M. Reddy
1994On Testing Wave Pipelined Circuits.
Jui-Ching Shyur, Hung-Pin Chen, Tai-Ming Parng
1994On the Computation of the Set of Reachable States of Hybrid Models.
A. S. Krishnakumar, Kwang-Ting Cheng
1994Optimizing Resource Utilization and Testability Using Hot Potato Techniques.
Miodrag Potkonjak, Sujit Dey
1994Optimum Functional Decomposition Using Encoding.
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994PESDA and Design Abstraction: How High is Up? (Panel).
Geoffrey Bunza, Steve Schulz, Tommy Jansson, Alex Silbey, Steve Ma, Edward H. Frank
1994Panel: Complex System Verification: The Challenge Ahead.
Ronald Collett, Mike Gianfagna, Michel Courtoy, Martin Baynes, Johan Van Ginderdeuren, Kenneth L. McMillan, Stephen Ricca, Alberto L. Sangiovanni-Vincentelli, Steve Sapiro, Naeem Zafar
1994Partitioning Very Large Circuits Using Analytical Placement Techniques.
Bernhard M. Riess, Konrad Doll, Frank M. Johannes
1994Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards.
Sean Murphy
1994Path Hashing to Accelerate Delay Fault Simulation.
Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
1994Performance Analysis Based on Timing Simulation.
Christian D. Nielsen, Michael Kishinevsky
1994Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994Performance Optimization Using Exact Sensitization.
Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994Performance-Driven Simultaneous Place and Route for Row-Based FPGAs.
Sudip Nag, Rob A. Rutenbar
1994Permissible Observability Relations in FSM Networks.
Huey-Yih Wang, Robert K. Brayton
1994Placement and Routing for a Field Programmable Multi-Chip Module.
Sanko Lan, Avi Ziv, Abbas El Gamal
1994Probabilistic Analysis of Large Finite State Machines.
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
1994Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994.
Michael J. Lorenzetti
1994ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation.
Steven Parkes, Prithviraj Banerjee, Janak H. Patel
1994Protocol Generation for Communication Channels.
Sanjiv Narayan, Daniel Gajski
1994RC Interconnect Optimization Under the Elmore Delay Model.
Sachin S. Sapatnekar
1994Random Generation of Test Instances for Logic Optimizers.
Kazuo Iwama, Kensuke Hino
1994Rapid Prototyping of ASIC Based Systems.
Patrick H. Kelly, Kevin J. Page, Paul M. Chau
1994Rectification of Multiple Logic Design Errors in Multiple Output Circuits.
Masahiro Tomita, Tamotsu Yamamoto, Fuminori Sumikawa, Kotaro Hirano
1994Rectilinear Steiner Trees with Minimum Elmore Delay.
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
1994Resynthesis and Retiming for Optimum Partial Scan.
Srimat T. Chakradhar, Sujit Dey
1994Routing for Manufacturability.
Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
1994Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture.
Yachyang Sun, C. L. Liu
1994Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms.
Mohammed Aloqeely, C. Y. Roger Chen
1994Sequential Circuit Test Generation in a Genetic Algorithm Framework.
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
1994Simultaneous Placement and Module Optimization of Analog IC's.
Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli
1994Software Patents and Their Potential Impact on the EDA Community (Panel).
William M. van Cleemput, Ewald Detjens, Herman Beke, George C. Chen, Joseph Hustein, William Lattin, Dennis S. Fernandez
1994Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems.
Pai H. Chou, Gaetano Borriello
1994Statistical Delay Modeling in Logic Design and Synthesis.
Horng-Fei Jyu, Sharad Malik
1994Statistical Estimation of the Switching Activity in Digital Circuits.
Michael G. Xakellis, Farid N. Najm
1994Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits.
Sharad Mehrotra, Paul D. Franzon, Wentai Liu
1994Structured Design Methodology for High-Level Design.
Polen Kission, Hong Ding, Ahmed Amine Jerraya
1994Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs.
Kai Zhu, D. F. Wong
1994Synthesis of Instruction Sets for Pipelined Microprocessors.
Ing-Jer Huang, Alvin M. Despain
1994Technology Mapping Using Fuzzy Logic.
Sasan Iman, Massoud Pedram, Kamal Chaudhary
1994Technology Summit - A View from the Top (Panel).
Andrew J. Graham, Richard Goldman, Wen-Tsuen Chen, Kerry Hanson, Nikolay G. Malishev, Shin-ichi Nakayama
1994The AT&T 5ESS Hardware Design Environment: A Large System's Hardware design Process.
Kenneth A. Radtke
1994The Attributed-Behavior Abstraction and Synthesis Tools.
Lawrence F. Arnstein, Donald E. Thomas
1994The Design of High-Performance Microprocessors at Digital.
Thomas F. Fox
1994The Minimization and Decomposition of Interface State Machines.
Ajay J. Daga, William P. Birmingham
1994The Use of CAD Frameworks in a CIM Environment.
Wang Tek Kee, Dennis Sng, Jacob Gan, Low Kin Kiong
1994Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation.
Chung-Jung Chen, Wu-Shiung Feng
1994VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults.
Takaharu Nagumo, Masahiko Nagai, Takao Nishida, Masayuki Miyoshi, Shunsuke Miyamoto