| 1993 | A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules. Tsu-Chang Lee |
| 1993 | A Clustering-Based Optimization Algorithm in Zero-Skew Routings. Masato Edahiro |
| 1993 | A Compaction Method for Full Chip VLSI Layouts. Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori |
| 1993 | A Cost-Based Approach to Partial Scan. Prashant S. Parikh, Miron Abramovici |
| 1993 | A Cross-Debugging Method for Hardware/Software Co-design Environments. Yehuda Kra |
| 1993 | A Layout Estimation Algorithm for RTL Datapaths. Mehrdad Nourani, Christos A. Papachristou |
| 1993 | A Negative Reinforcement Method for PGA Routing. Forbes D. Lewis, Wang Chia-Chi Pong |
| 1993 | A New Optimizer for Performance Optimization of Analog Integrated Circuits. N. S. Nagaraj |
| 1993 | A New Viewpoint on Two-Level Logic Minimization. Olivier Coudert, Jean Christophe Madre, Henri Fraisse |
| 1993 | A Nuffer Distribution Algorithm for High-Speed Clock Routing. Jun Dong Cho, Majid Sarrafzadeh |
| 1993 | A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. Jason Cong, M'Lissa Smith |
| 1993 | A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem. Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu |
| 1993 | A State Traversal Algorithm Using a State Covariance Matrix. Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin |
| 1993 | A Tree-Based Scheduling Algorithm for Control-Dominated Circuits. S. H. Huang, Y. L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang |
| 1993 | A Unified Approach to Language Containment and Fair CTL Model Checking. Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan |
| 1993 | A Verification Technique for Gated Clock. Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ABLE: AMD Backplane for Layout Engines. Kenneth W. Wan, Roshan A. Gidwani |
| 1993 | Active Documentation: A New Interface for VLSI Design. Mário J. Silva, Randy H. Katz |
| 1993 | Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation. Eli Chiprout, Michel S. Nakhla |
| 1993 | Algorithms for Approximate FSM Traversal. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi |
| 1993 | An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. Sreejit Chakravarty, Yiming Gong |
| 1993 | An Approach for Redesigning in Data Path Synthesis. Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani |
| 1993 | An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. Abhijit Chatterjee, Rabindra K. Roy |
| 1993 | An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines. Tam Anh Chu, Narayana Mani, Clement K. C. Leung |
| 1993 | An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.. Nam Sung Woo, Jaeseok Kim |
| 1993 | An Efficient Multilayer MCM Router Based on Four-Via Routing. Kei-Yong Khoo, Jason Cong |
| 1993 | An Efficient Non-Quasi-Static Diode Model for Circuit Simulation. Andrew T. Yang, Yu Liu, Jack T. Yao, R. R. Daniels |
| 1993 | An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer |
| 1993 | An Efficient Timing-Driven Global Routing Algorithm. Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh |
| 1993 | An Information Model of Time. Cristian A. Giumale, Hilary J. Kahn |
| 1993 | Analog System Verification in the Presence of Parasitics Using Behavioral Simulation. Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections. Monjurul Haque, Salim Chowdhury |
| 1993 | Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy |
| 1993 | Are EDA Platform Preferences About to Shift? (Panel Abstract). William S. Johnson |
| 1993 | Automatic Functional Test Generation Using the Extended Finite State Machine Model. Kwang-Ting Cheng, A. S. Krishnakumar |
| 1993 | Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. Polly Siegel, Giovanni De Micheli, David L. Dill |
| 1993 | BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
| 1993 | Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf |
| 1993 | Bridge Fault simulation strategies for CMOS integrated Circuits. Brian Chess, Tracy Larrabee |
| 1993 | Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo |
| 1993 | Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Comparative Design Validation Based on Event Pattern Mappings. Benoit A. Gennart |
| 1993 | Cooperative Approach to a Practical Analog LSI Layout System. Masato Mogaki, Yoichi Shiraishi, Mitsuyuki Kimura, Tetsuro Hino |
| 1993 | Cost Minimization of Partitions into Multiple Devices. Roman Kuznar, Franc Brglez, Krzysztof Kozminski |
| 1993 | Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy |
| 1993 | Critical Path Minimization Using Retiming and Algebraic Speed-Up. Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker |
| 1993 | DRAFTS: Discretized Analog Circuit Fault Simulator. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham |
| 1993 | Delay Fault Coverage and Performance Tradeoffs. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Design Management Using Dynamically Defined Flows. Peter R. Sutton, Jay B. Brockman, Stephen W. Director |
| 1993 | Design for Testability for Path Delay faults in Sequential Circuits. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1993 | Diagnosis and Correction of Logic Design Errors in Digital Circuits. Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj |
| 1993 | Elimination of Dynamic hazards by Factoring. Cho W. Moon, Robert K. Brayton |
| 1993 | Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box? (Panel Abstract). Wayne H. Wolf |
| 1993 | Espresso-Signature: A New Exact Minimizer for Logic Functions. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Estimating Architectural Resources and Performance for High-Level Synthesis Applications. Alok Sharma, Rajiv Jain |
| 1993 | Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh |
| 1993 | Experiences in Functional Validation of a High Level Synthesis System. Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru |
| 1993 | Fast Approximation of the Transient Response of Lossy Transmision Line Trees. Mysore Sriram, Sung-Mo Kang |
| 1993 | Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. Wolfgang Meyer, Raul Camposano |
| 1993 | FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program. Mattan Kamon, Michael J. Tsuk, Jacob White |
| 1993 | Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits. Hansruedi Heeb, Saila Ponnapalli, Albert E. Ruehli |
| 1993 | Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. Charles J. Alpert, Andrew B. Kahng |
| 1993 | HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. Glenn G. Lai, Donald S. Fussell, D. F. Wong |
| 1993 | High-Level Symbolic Construction Technique for High Performance Sequential Synthesis. Andrew Seawright, Forrest Brewer |
| 1993 | High-Level Synthesis of Fault-Secure Microarchitectures. Ramesh Karri, Alex Orailoglu |
| 1993 | High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu |
| 1993 | High-Level Transformations for Minimizing Syntactic Variances. Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran |
| 1993 | High-Performance Routing Trees With Identified Critical Sinks. Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins |
| 1993 | High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods. Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes |
| 1993 | Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich |
| 1993 | Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. Georgios I. Stamoulis, Ibrahim N. Hajj |
| 1993 | InSyn: Integrated Scheduling for DSP Applications. Alok Sharma, Rajiv Jain |
| 1993 | Increasing Design Quality and Engineering Productivity through Design Reuse. Emil F. Girczyc, Steve Carlson |
| 1993 | Incremental Event-Driven Simulation of Digital FET Circuits. Chandramouli Visweswariah, Jalal A. Wehbeh |
| 1993 | Information Modelling of EDIF. Rachel Y. W. Lau, Hilary J. Kahn |
| 1993 | Iterative Wirability and Performance Improvement for FPGAs. Sudip Nag, Kaushik Roy |
| 1993 | Life Expectancy of Standards (Panel Abstract). Stephen R. Pollock |
| 1993 | Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. Jeffrey J. Joyce, Carl-Johan H. Seger |
| 1993 | Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). Jonathan Rose |
| 1993 | MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. Mahesh Mehendale |
| 1993 | MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. Cyrus Bamji, Ravi Varadarajan |
| 1993 | Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract). Michael C. McFarland |
| 1993 | Minimal Shift Counters and Frequency Division. Alice M. Tokarnia |
| 1993 | Minimum Length Synchronizing Sequences of Finite State Machine. June-Kyung Rho, Fabio Somenzi, Carl Pixley |
| 1993 | Multi-vendor Tool Integration Experiences (Panel Abstract). Ronald Collett |
| 1993 | NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri |
| 1993 | Non-Scan Design-for-Testability Techniques for Sequential Circuits. Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel |
| 1993 | On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. Jason Cong, Yuzheng Ding |
| 1993 | On Computing the Transitive Closure of a State Transition Relation. Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton |
| 1993 | On Routability Prediction for Field-Programmable Gate Arrays. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
| 1993 | Optimal Clustering for Delay Minimization. Rajmohan Rajaraman, D. F. Wong |
| 1993 | Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Peichen Pan, Sai-keung Dong, C. L. Liu |
| 1993 | Optimization and Resynthesis of Complex Data-Paths. Hans Eveking, Stefan Höreth |
| 1993 | Optimization of Combinational Logic Circuits Based on Compatible Gates. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli |
| 1993 | Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. Régis Leveugle |
| 1993 | Partial Scan with Retiming. Dimitrios Kagaris, Spyros Tragoudas |
| 1993 | Performance Directed Technology Mapping for Look-Up Table Based FPGAs. Prashant Sawkar, Donald E. Thomas |
| 1993 | Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. Bradley S. Carlson, C. Y. Roger Chen |
| 1993 | Performance Oriented Rectilinear Steiner Trees. Andrew Lim, Siu-Wing Cheng, Ching-Ting Wu |
| 1993 | Performance Specification Using Attributed Grammars. Ram Mandayam, Ranga Vemuri |
| 1993 | Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. Abhijit Dharchoudhury, Sung-Mo Kang |
| 1993 | Performance-Driven Interconnect Design Based on Distributed RC Delay Model. Jason Cong, Kwok-Shing Leung, Dian Zhou |
| 1993 | Performance-Driven Steiner Tree Algorithm for Global Routing. Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang |
| 1993 | Practical Statistical Design of Complex Integrated Circuit Products. Steven G. Duvall |
| 1993 | Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993. Alfred E. Dunlop |
| 1993 | Quadratic Boolean Programming for Performance-Driven System Partitioning. Minshine Shih, Ernest S. Kuh |
| 1993 | Reducing BDD Size by Exploiting Functional Dependencies. Alan J. Hu, David L. Dill |
| 1993 | Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage |
| 1993 | Resistance Extraction using a Routing Algorithm. Lorenz Ladage, Rainer Leupers |
| 1993 | Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj |
| 1993 | Resynthesis of Multi-Phase Pipelines. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Rotation Scheduling: A Loop Pipelining Algorithm. Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha |
| 1993 | Routability-Driven Fanout Optimization. Hirendu Vaishnav, Massoud Pedram |
| 1993 | S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function. Haifang Liao, Wayne Wei-Ming Dai, Rui Wang, Fung-Yuel Chang |
| 1993 | Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. Gopi Ganapathy, Jacob A. Abraham |
| 1993 | Sequential Circuit Delay optimization Using Global Path Delays. Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler |
| 1993 | Sequential Circuit Test Generation on a Distributed System. Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo |
| 1993 | Sequential Synthesis for Table Look Up Programmable Gate Arrays. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | Spectral Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
| 1993 | Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, Jerry Chih-Yuan Yang |
| 1993 | Speed up of Behavioral A.T.P.G. using a Heuristic Criterion. Jean François Santucci, Anne-Lise Courbis, Norbert Giambiasi |
| 1993 | SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather |
| 1993 | Synthesis of Pipelined Instruction Set Processors. Richard J. Cloutier, Donald E. Thomas |
| 1993 | TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. Marios C. Papaefthymiou, Keith H. Randall |
| 1993 | Technology Decomposition and Mapping Targeting Low Power Dissipation. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain |
| 1993 | Technology Mapping for Lower Power. Vivek Tiwari, Pranav Ashar, Sharad Malik |
| 1993 | The Clinton/Gore Technology Policies. Ralph D. Nurnberger |
| 1993 | The Key to EDA Results: Component & Library Management (Panel Abstract). Romesh Wadhwani |
| 1993 | The Sea-of-Wires Array Aynthesis System. Ing-Yi Chen, Geng-Lin Chen, Fredrick J. Hill, Sy-Yen Kuo |
| 1993 | The State of CAD and VLSI in Russia. Valery Yarnikh |
| 1993 | The State of EDA in Russian Universities. Valery M. Mikhov |
| 1993 | The State of Simulation in Russia. Alexander Birger |
| 1993 | The State of VHDL in Russia. Yuri Tatarnikov |
| 1993 | Timing Optimization By Gate Resizing And Critical Path Identification. Wen-Ben Jone, Chen-Liang Fang |
| 1993 | Towards Optimal System-Level Design. Manjote S. Haworth, William P. Birmingham |
| 1993 | Utilization of Multiport Memories in Data Path Synthesis. Taewhan Kim, C. L. Liu |
| 1993 | VIPER: An Efficient Vigorously Sensitizable Path Extractor. Hoon Chang, Jacob A. Abraham |
| 1993 | What is the Next Big Productivity Boost for Designers? (Panel Abstract). Kurt Keutzer |
| 1993 | Where in the World Should CAD Software be Made? (Panel Abstract). John A. Darringer |
| 1993 | Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems. Shin-ichi Minato |