| 1990 | A Channel/Switchbox Definition Algorithm for Building-Block Layout. Yang Cai, D. F. Wong |
| 1990 | A Data Path Layout Assembler for High Performance DSP Circuits. H. Cai, Stefaan Note, Paul Six, Hugo De Man |
| 1990 | A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. John P. Fishburn |
| 1990 | A Fault Analysis Method for Synchronous Sequential Circuits. Tah-Yuan Kuo, Jau-Yien Lee, Jhing-Fa Wang |
| 1990 | A Framework for Industrial Layout Generators. Wayne Bower, Carl Seaquist, Wayne H. Wolf |
| 1990 | A Generalized Interconnect Model for Data Path Synthesis. Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc |
| 1990 | A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System. Nam Sung Woo |
| 1990 | A Gridless Router for Industrial Design Rules. Werner L. Schiele, Thomas Krüger, Knut M. Just, F. H. Kirsch |
| 1990 | A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki |
| 1990 | A Heuristic Algorithm for the Fanout Problem. Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli |
| 1990 | A Hierarchy Preserving Hierarchical Compactor. David Marple |
| 1990 | A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. Christos A. Papachristou, Haluk Konuk |
| 1990 | A Multi-Layer Router Utilizing Over-Cell Areas. Evagelos Katsadas, Edwin Kinnen |
| 1990 | A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint. Masayuki Terai, Kazuhiro Takahashi, Koji Sato |
| 1990 | A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing. Abhijit Chatterjee, Richard I. Hartley |
| 1990 | A Parallel Pattern Mixed-Level Fault Simulator. Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu |
| 1990 | A Practical Online Design Rule Checking System. Goro Suzuki, Yoshio Okamura |
| 1990 | A Transistor Reordering Technique for Gate Matrix Layout. Uminder Singh, C. Y. Roger Chen |
| 1990 | A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1990 | A Variable Observation Time Method for Testing Delay Faults. Weiwei Mao, Michael D. Ciletti |
| 1990 | ASSURE: Automated Design for Dependability. Patrick Edmond, Anurag P. Gupta, Daniel P. Siewiorek, Audrey A. Brennan |
| 1990 | Abstract Data Types and High-Level Synthesis. Gregory S. Whitcomb, A. Richard Newton |
| 1990 | Algorithms for Library-Specific Sizing of Combinational Logic. Pak K. Chan |
| 1990 | An Adaptive Timing-Driven Layout for High Speed VLSI. Suphachai Sutanthavibul, Eugene Shragowitz |
| 1990 | An Analytical Approach to Floorplan Design and Optimization. Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen |
| 1990 | An Efficient Delay Test Generation System for Combinational Logic Circuits. Eun Sei Park, M. Ray Mercer |
| 1990 | An Entropy Measure for the Complexity of Multi-Output Boolean Functions. Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1990 | An Intelligent Component Database for Behavioral Synthesis. Gwo-Dong Chen, Daniel Gajski |
| 1990 | An Intermediate Representation for Behavioral Synthesis. Nikil D. Dutt, Tedd Hadley, Daniel Gajski |
| 1990 | An O( Chi-Yuan Lo, Ravi Varadarajan |
| 1990 | An Object-Oriented Kernel for an Integrated Design and Process Planning System. S. J. Feghhi, Michael M. Marefat, Rangasami L. Kashyap |
| 1990 | An Object-Oriented VHDL Design Environment. Moon-Jung Chung, Sangchul Kim |
| 1990 | An Optimal Algorithm for Floorplan Area Optimization. Ting-Chi Wang, D. F. Wong |
| 1990 | Analysis and Design of Latch-Controlled Synchronous Digital Circuits. Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun |
| 1990 | Architecture Synthesis of High-Performance Application-Specific Processors. Maurício Breternitz Jr., John Paul Shen |
| 1990 | Automatic Incorporation of On-Chip Testability Circuits. Noriyuki Ito |
| 1990 | Automatic Operator Configuration in the Synthesis of Pipelined Architectures. Kristen N. McNall, Albert E. Casavant |
| 1990 | Automatic Test Generation Using Quadratic 0-1 Programming. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
| 1990 | BIST PLAs, Pass or Fail - A Case Study. Shambhu J. Upadhyaya, John A. Thodiyil |
| 1990 | BREL - a Prolog Knowledge-based System Shell for VLSI CAD. Marwan A. Jabri |
| 1990 | Behavioral Fault Simulation in VHDL. P. C. Ward, James R. Armstrong |
| 1990 | Benchmarks for Cell Synthesis. Dwight D. Hill, Bryan Preas |
| 1990 | Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita |
| 1990 | Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. Robert J. Francis, Jonathan Rose, Kevin Chung |
| 1990 | Circuit Extraction on a Message-Based Multiprocessor. Bruce A. Tonkin |
| 1990 | Clock Routing for High-Performance ICs. Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh |
| 1990 | Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima |
| 1990 | Comparing Structurally Different Views of a VLSI Design. Mike Spreitzer |
| 1990 | Constraint Generation for Routing Analog Circuits. Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Corolla Based Circuit Partitioning and Resynthesis. Sujit Dey, Franc Brglez, Gershon Kedem |
| 1990 | Data Path Allocation Based on Bipartite Weighted Matching. Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu |
| 1990 | Data Path Tradeoffs Using MABAL. Kayhan Küçükçakar, Alice C. Parker |
| 1990 | Datapath Generator Based on Gate-Level Symbolic Layout. Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori |
| 1990 | Delay and Area Optimization in Standard-Cell Design. Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh |
| 1990 | Design Data Management in a CAD Framework Environment. Lung-Chun Liu |
| 1990 | Design Management Based on Design Traces. Andrea Casotto, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Design Methodology Management - a CAD Framework Initiative Perspective. Kenneth W. Fiduk, Sally Kleinfeldt, Marta Kosarchyn, Eileen B. Perez |
| 1990 | Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. Erik C. Carlson, Rob A. Rutenbar |
| 1990 | Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang |
| 1990 | Distributed Computing Environment for Design Automation in the 90's (Panel Abstract). Basant R. Chawla |
| 1990 | Distributed and Parallel Demand Driven Logic Simulation. Krishnamurthy Subramanian, Mehdi R. Zargham |
| 1990 | EST: The New Frontier in Automatic Test-Pattern Generation. John Giraldi, Michael L. Bushnell |
| 1990 | Efficient Implementation of a BDD Package. Karl S. Brace, Richard L. Rudell, Randal E. Bryant |
| 1990 | Extension of the Critical Path Tracing Algorithm. T. Ramakrishnan, L. Kinney |
| 1990 | Failure Recovery in the MICON System. Ajay J. Daga, William P. Birmingham |
| 1990 | General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. Jason Cong, Bryan Preas, C. L. Liu |
| 1990 | Global Hardware Synthesis from Behavioral Dataflow Descriptions. Josef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März |
| 1990 | Global Routing Considerations in a Cell Synthesis System. Dwight D. Hill, Don Shugard |
| 1990 | High-Level Synthesis: Technology Transfer to Industry. Robin C. Sarma, Mark D. Dooley, N. Craig Newman, Graham Hetherington |
| 1990 | Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract). Kurt Keutzer |
| 1990 | Integrated Placement for Mixed Macro Cell and Standard Cell Designs. Michael Upton, Khosrow Samii, Stephen Sugiyama |
| 1990 | Integration of Hardware and Software in Embedded Systems Design (Panel Abstract). William Lattin |
| 1990 | Is Redundancy Necessary to Reduce Delay. Kurt Keutzer, Sharad Malik, Alexander Saldanha |
| 1990 | LECSIM: A Levelized Event Driven Compiled Logic Simulation. Zhicheng Wang, Peter M. Maurer |
| 1990 | Layout Compaction with Attractive and Repulsive Constraints. Akira Onozawa |
| 1990 | Layout Optimization by Pattern Modification. Ramin Hojati |
| 1990 | Layout Synthesis of MOS Digital Cells. Antun Domic |
| 1990 | LiB: A Cell Layout Generator. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu |
| 1990 | Logic Optimization Algorithm by Linear Programming Approach. Naohiro Kageyama, Chihei Miura, Tsuguo Shimizu |
| 1990 | Logic Synthesis for Programmable Gate Arrays. Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. Daniel R. Brasen, Michael L. Bushnell |
| 1990 | MISER: An Integrated Three Layer Gridless Channel Router and Compactor. Roshan A. Gidwani, Naveed A. Sherwani |
| 1990 | Memory, Control and Communications Synthesis for Scheduled Algorithms. Douglas M. Grant, Peter B. Denyer |
| 1990 | Meta Data Management in the NELSIS CAD Framework. Pieter van der Wolf, G. W. Sloof, Peter Bingley, Patrick M. Dewilde |
| 1990 | Multilevel Synthesis Minimizing the Routing Factor. Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot |
| 1990 | NASFLOW, a Simulation Tool for Silicon Technology Development. D. David Forsythe, Atul P. Agarwal, Chune-Sin Yeh, Sheldon Aronowitz, Bhaskar Gadepally |
| 1990 | NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima |
| 1990 | New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion. Tsuneo Okubo, Takashi Watanabe, Kou Wada |
| 1990 | New Placement and Global Routing Algorithms for Standard Cell Layouts. Masato Edahiro, Takeshi Yoshimura |
| 1990 | Object Databases in Electronic Design: Implementation Experiences (Panel Abstract). Tim Andrews |
| 1990 | On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). Sreejit Chakravarty |
| 1990 | Optimization by Simulated Evolution with Applications to Standard Cell Placement. Ralph-Michael Kling, Prithviraj Banerjee |
| 1990 | Optimum and Heuristic Data Path Scheduling Under Resource Constraints. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin |
| 1990 | Organized C: A Unified Method of Handling Data in CAD Algorithms and Databases. Jiri Soukup |
| 1990 | PALACE: A Kayout Generator for SCVS Logic Blocks. Knut M. Just, Edgar Auer, Werner L. Schiele, Alexander Schwaferts |
| 1990 | PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors. Gung-Chung Yang |
| 1990 | PHIGURE: A Parallel Hierarchical Global Router. Randall J. Brouwer, Prithviraj Banerjee |
| 1990 | Pad Placement and Ring Routing for Custom Chip Layout. Deborah C. Wang |
| 1990 | Parallel Circuit Simulation Using Hierarchical Relaxation. Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh |
| 1990 | Percolation Based Synthesis. Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski |
| 1990 | Performance-Driven Constructive Placement. Ichiang Lin, David Hung-Chang Du |
| 1990 | Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990. Richard C. Smith |
| 1990 | Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel |
| 1990 | Reduced Offsets for Two-Level Multi-Valued Logic Minimization. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Relative Scheduling Under Timing Constraints. David C. Ku, Giovanni De Micheli |
| 1990 | SKILL: A CAD System Extension Language. Timothy J. Barnes |
| 1990 | SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. Hyung Ki Lee, Dong Sam Ha |
| 1990 | Segmented Channel Routing. Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal |
| 1990 | Sequential Circuit Verification Using Symbolic Model Checking. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill |
| 1990 | Sequential Test Generation at the Register-Transfer and Logic Levels. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima |
| 1990 | Speed Up of Test Generation Using High-Level Primitives. Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain |
| 1990 | Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract). A. Richard Newton |
| 1990 | Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. Youssef Saab, Vasant B. Rao |
| 1990 | Symbolic Simulation - Techniques and Applications. Randal E. Bryant |
| 1990 | Synthesis Using Path-Based scheduling: algorithms and Exercises. Raul Compasano, Reinaldo A. Bergamaschi |
| 1990 | Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. Srinivas Devadas, Kurt Keutzer |
| 1990 | System Simulation of Printed Circuit Boards Including Packages and Connectors. K. Adamiak, R. Allen, J. Poltz, C. Rebizant, A. Wexler |
| 1990 | Techniques for Unit-Delay Compiled Simulation. Peter M. Maurer, Zhicheng Wang |
| 1990 | Test Function Specification in Synthesis. Vishwani D. Agrawal, Kwang-Ting Cheng |
| 1990 | Testing Strategies for the 1990's (Panel Abstract). Alberto L. Sangiovanni-Vincentelli |
| 1990 | The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. Richard J. Cloutier, Donald E. Thomas |
| 1990 | The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines. Wayne H. Wolf |
| 1990 | The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. Kenneth M. Butler, M. Ray Mercer |
| 1990 | The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. Hamid Savoj, Robert K. Brayton |
| 1990 | The VHDL Validation Suite. James Armstrong, Chang H. Cho, Sandeep Shah, Chakravarthy Kosaraju |
| 1990 | Timing Analysis in Precharge/Unate Networks. Patrick C. McGeer, Robert K. Brayton |
| 1990 | Timing Driven Placement Using Complete Path Delays. Wilm E. Donath, Reini J. Norman, Bhuwan K. Agrawal, Stephen E. Bello, Sang-Yong Han, Jerome M. Kurtzberg, Paul Lowy, Roger I. McMillan |
| 1990 | Timing Optimization for Multi-Level Combinational Networks. Kuang-Chien Chen, Saburo Muroga |
| 1990 | Timing Verification Using HDTV. Alan R. Martello, Steven P. Levitan, Donald M. Chiarulli |
| 1990 | Verification of Interacting Sequential Circuits. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | Waveform Moment Methods for Improved Interconnection Analysis. Steven Paul McCormick, Jonathan Allen |
| 1990 | Women in the Microelectronics Industry (Panel Abstract). Petra Michel |