| 1989 | A Comparison of Four Two-dimensional Gate Matrix Layout Tools. Mary Jane Irwin, Robert Michael Owens |
| 1989 | A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. Wen-Ben Jone, Christos A. Papachristou |
| 1989 | A Deterministic Approach to Adjacency Testing for Delay Faults. C. Thomas Glover, M. Ray Mercer |
| 1989 | A Framework for Scheduling Multi-Rate Circuit Simulation. Antony P.-C. Ng, V. Visvanathan |
| 1989 | A Functional-Level Test Generation Methodology Using Two-level Representations. Utpal J. Davé, Janak H. Patel |
| 1989 | A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. Vinod Narayanan, Vijay Pitchumani |
| 1989 | A Module Generator for Optimized CMOS Buffers. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili |
| 1989 | A Neural Network Design for Circuit Partitioning. Jih-Shyr Yih, Pinaki Mazumder |
| 1989 | A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits. Jhing-Fa Wang, Tah-Yuan Kuo, Jau-Yien Lee |
| 1989 | A New Approach to the Rectilinear Steiner Tree Problem. Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong |
| 1989 | A New Heuristic for Single Row Routing Problems. Naveed A. Sherwani, Jitender S. Deogun |
| 1989 | A New Model for the High Level Description and Simulation of VLSI Networks. A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick M. Dewilde |
| 1989 | A Note on Clustering Modules for Floorplanning. John D. Gabbe, P. A. Subrahmanyam |
| 1989 | A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators. Zhiping Yu, Weijian Zhao, Zhilian Yang, Y. Edmund Lien |
| 1989 | A Novel Approach to Accurate Timing Verification Using RTL Descriptions. Kaushik Roy, Jacob A. Abraham |
| 1989 | A Parallel Branch and Bound Algorithm for Test Generation. Srinivas Patil, Prithviraj Banerjee |
| 1989 | A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. Jeff S. Sargent, Prithviraj Banerjee |
| 1989 | A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs. Miodrag Potkonjak, Jan M. Rabaey |
| 1989 | A Scheme for Overlaying Concurrent Testing of VLSI Circuits. Wen-Ben Jone, Christos A. Papachristou, M. Pereira |
| 1989 | A Simplified Six-waveform Type Method for Delay Fault Testing. Weiwei Mao, Michael D. Ciletti |
| 1989 | A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD. Meng-Lin Yu |
| 1989 | A Technology-adaptive Allocation of Functional Units and Connections. Nam Sung Woo, Hyunchul Shin |
| 1989 | A Unified Data Exchange Environment Based on EDIF. Wanhao Li, Hart Switzer |
| 1989 | A Unified Design Representation Can Work. Paul Kollaritsch, Steve Lusky, Doug Matzke, Derek Smith, Paul Stanford |
| 1989 | ACE: A Hierarchical Graphical Interface for Architectual Synthesis. O. A. Buset, Mohamed I. Elmasry |
| 1989 | ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation. Bulent I. Dervisoglu, M. A. Keil |
| 1989 | AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer |
| 1989 | Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. Prathima Agrawal, Raffi Tutundjian, William J. Dally |
| 1989 | An ASIC Methodology for Mixed Analog-Digital Simulation. Michael Rumsey, John Sackett |
| 1989 | An Analytic Optimization Technique for Placement of Macro-Cells. Alexander Herrigel, Wolfgang Fichtner |
| 1989 | An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules. Klaus D. Müller-Glaser, Jürgen Bortolazzi |
| 1989 | An Automatic Test Generation Algorithm for Hardware Description Languages. F. E. Norrod |
| 1989 | An Efficient Finite Element Method for Submicron IC Capacitance Extraction. N. P. van der Meijs, Arjan J. van Genderen |
| 1989 | An Efficient Two-Dimensional Layout Compaction Algorithm. Hyunchul Shin, Chi-Yuan Lo |
| 1989 | An Evolution-Based Approach to Partitioning ASIC Systems. Youssef Saab, Vasant B. Rao |
| 1989 | An Interactive Tool for Register-level Structure Optimization. David Knapp |
| 1989 | An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. Sarma Sastry, Jen-I Pi |
| 1989 | An O(nlogm) Algorithm for VLSI Design Rule Checking. Charles R. Bonapace, Chi-Yuan Lo |
| 1989 | An Object Oriented Approach to CAD Tool Control within a Design Framework. James Daniell, Stephen W. Director |
| 1989 | An Object-Oriented Datamodel for the VLSI Design System PLAYOUT. Ernst Siepmann, Gerhard Zimmermann |
| 1989 | Approaches to Multi-level Sequential Logic Synthesis. Srinivas Devadas |
| 1989 | Architectural Partitioning for System Level Design. Elizabeth D. Lagnese, Donald E. Thomas |
| 1989 | Automatic Generation of Behavioral Models from Switch-Level Descriptions. David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh |
| 1989 | Automatic Layout of Silicon-on-Silicon Hybrid Packages. Bryan Preas, Massoud Pedram, Don Curry |
| 1989 | Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions. Sally A. Hayati, Alice C. Parker |
| 1989 | Automatic Sizing of Power/Ground (P/G) Networks in VLSI. Rajiv Dutta, Malgorzata Marek-Sadowska |
| 1989 | Automatic Synthesis of Boolean Equations Using Programmable Array Logic. Rajeev Goré, Kotagiri Ramamohanarao |
| 1989 | Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions. Anshul Kumar, Shashi Kumar, P. Kulshreshtha, Sudipto Ghose |
| 1989 | Automatic Tub Region Generation for Symbolic Layout Compaction. Chi-Yuan Lo |
| 1989 | Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. Carol V. Gura, Jacob A. Abraham |
| 1989 | Behavioral Modeling of Transmission Gates in VHDL. Steven S. Leung |
| 1989 | CASE Environments for Design Automation. Anthony I. Wasserman |
| 1989 | CEDIF: A Data Driven EDIF Reader. Mark Roberts |
| 1989 | CMOS Stuck-open Fault Detection Using Single Test Patterns. Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya |
| 1989 | COMP: A VHDL Composition System. Paul R. Jordan, Ronald D. Williams |
| 1989 | Capturing Designer Expertise the CGEN System. William P. Birmingham, Daniel P. Siewiorek |
| 1989 | Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation. Larry Soulé, Anoop Gupta |
| 1989 | Compaction of a Routed Channel on the Connection Machine. Shantanu Ganguly, Vijay Pitchumani |
| 1989 | Computing Signal Delay in General RC Networks by Tree/Link Partitioning. Pak K. Chan, Kevin Karplus |
| 1989 | CrossCheck: A Cell Based VLSI Testability Solution. T. Ghewala |
| 1989 | DTR: A Defect-Tolerant Routing Algorithm. Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi |
| 1989 | DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions. Yasuyuki Fujihara, Yutaka Sekiyama, Yasuo Ishibashi, Masao Yanaka |
| 1989 | Data Parallel Simulation Using Time-Warp on the Connection Machine. Moon-Jung Chung, Y. Chung |
| 1989 | Database Support for Evolving Design Objects. Alexandros Biliris |
| 1989 | DeBuMA: Description, Building and Management of Applications. Claudia S. Frydman, Norbert Giambiasi, M. Gatumel, P. Bayle |
| 1989 | Design for Manufacturability and Yield. Andrzej J. Strojwas |
| 1989 | Designer Controlled Behavioral Synthesis. Nikil D. Dutt, Daniel Gajski |
| 1989 | Differential Fault Simulation - a Fast Method Using Minimal Memory. Wu-Tung Cheng, Meng-Lin Yu |
| 1989 | ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. Dorothy E. Setliff, Rob A. Rutenbar |
| 1989 | Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. Patrick C. McGeer, Robert K. Brayton |
| 1989 | Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis. S. H. Yen, David Hung-Chang Du, Subbarao Ghanta |
| 1989 | Efficient Final Placement Based on Nets-as-Points. Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer |
| 1989 | Efficient Floorplan Area Optimization. D. F. Wong, P. S. Sakhamuri |
| 1989 | Efficient Prime Factorization of Logic Expressions. Patrick C. McGeer, Robert K. Brayton |
| 1989 | Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. P. Sadayappan, V. Visvanathan |
| 1989 | Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man |
| 1989 | Evaluating Hardware Models in DIGITAL's System Simulation Environment. A. K. George |
| 1989 | Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench. David L. Hwang, Thomas L. Wernimont, W. Kent Fuchs |
| 1989 | Experience with ADAM Synthesis System. Rajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker |
| 1989 | Experience with D-BUS Architecture for a Design Automation Framework. E. C. VanHorn, Roy R. Rezac |
| 1989 | Extracting Schematic-like Information from CMOS Circuit Net-lists. Wen-Jeng Lue, Lawrence P. McNamee |
| 1989 | FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. William D. Smith, David A. Duff, Martin Dragomirecky, James L. Caldwell, Michael J. Hartman, Jeffrey R. Jasica, Manuel A. d'Abreu |
| 1989 | FACET: A CAE System for RF Analogue Simulation Including Layout. R. F. Milsom, K. J. Scott, S. G. Clark, J. C. McEntegart, S. Ahmed, F. N. Soper |
| 1989 | Fast Hypergraph Partition. Andrew B. Kahng |
| 1989 | Fast Online/Offline Netlist Compilation of Hierarchical Schematics. Larry G. Jones |
| 1989 | Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. Patrick Odent, Luc J. M. Claesen, Hugo De Man |
| 1989 | From Network to Artwork. Leon Stok, G. P. Koster |
| 1989 | GABRIEL: A Design Environment for Programmable DSPs. Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt |
| 1989 | GENAC: An Automatic Cell Synthesis Tool. Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo |
| 1989 | GRASP: A Grammar-based Schematic Parser. Cyrus Bamji, Jonathan Allen |
| 1989 | Gate Matrix Layout Synthesis with Two-Dimensional Folding. Ichiang Lin, David Hung-Chang Du, Steve H.-C. Yen |
| 1989 | General Decomposition of Sequential Machines: Relationships to State Assignment. Srinivas Devadas |
| 1989 | High-Level Graphical User Interface Management in the FACE Synthesis Environment. Martin Dragomirecky, Ephraim P. Glinert, Jeffrey R. Jasica, David A. Duff, William D. Smith, Manuel A. d'Abreu |
| 1989 | Horizontal Partitioning of PLA-based Finite State Machines. Pierre G. Paulin |
| 1989 | IRSIM: An Incremental MOS Switch-Level Simulator. A. Salz, Mark Horowitz |
| 1989 | Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms. Thang Nguyen Bui, C. Heigham, Curt Jones, Frank Thomson Leighton |
| 1989 | Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. M. Balakrishnan, Peter Marwedel |
| 1989 | LASSIE: Structure to Layout for Behavioral Synthesis Tools. M. T. Trick, Stephen W. Director |
| 1989 | Locating Functional Errors in Logic Circuits. Kensaburo Alfredo Tamura |
| 1989 | Loop Optimization in Register-Transfer Scheduling for DSP-Systems. Gert Goossens, Joos Vandewalle, Hugo De Man |
| 1989 | MIOS: A Flexible System for PCB Manufacturing. Aangelo C. Hung, Philip M. Reddy, Paul J. Hammer |
| 1989 | MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai |
| 1989 | Massively Parallel Switch-Level Simulation: A Feasibility Study. Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar |
| 1989 | Min-cost Partitioning on a Tree Structure and Applications. Gopalakrishnan Vijayan |
| 1989 | Multi Chip Modules. R. H. Bruce, W. P. Meuli, J. Ho |
| 1989 | Multi-Level Logic Synthesis Using Communication Complexity. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
| 1989 | Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout. Wing K. Luk, Alvar A. Dean |
| 1989 | Multi-level Logic Simplification Using Don't Cares and Filters. Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1989 | NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations. Tiziano Villa, Alberto L. Sangiovanni-Vincentelli |
| 1989 | New Methods in the Analysis of Logic Minimization Data and Algorithms. Alan J. Coppola |
| 1989 | ORCA a Sea-of-Gates Place and Route System. Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli |
| 1989 | On Global Wire Ordering for Macro-Cell Routing. P. Groenveld |
| 1989 | On the General False Path Problem in Timing Analysis. David Hung-Chang Du, S. H. Yen, Subbarao Ghanta |
| 1989 | On the Repair of Redundant RAMs. V. G. Hemmady, Sudhakar M. Reddy |
| 1989 | Optimum Design of Reliable IC Power Networks Having General Graph Topologies. S. Chowdhury |
| 1989 | PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System. Marwan A. Jabri, David J. Skellern |
| 1989 | Parallel Pattern Fault Simulation of Path Delay Faults. Michael H. Schulz, Franz Fink, Karl Fuchs |
| 1989 | Partitioning by Probability Condensation. J. Blanks |
| 1989 | Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement. Somchai Prasitjutrakul, William J. Kubitz |
| 1989 | Performance optimized floor planning by graph planarization. B. Lokanathan, Edwin Kinnen |
| 1989 | Performance-driven Placement of Cell Based IC's. Michael A. B. Jackson, Ernest S. Kuh |
| 1989 | Plowing: Modifying Cells and Routing 45: 9D - Layouts. Knut M. Just, Werner L. Schiele, Thomas Krüger |
| 1989 | Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989. Donald E. Thomas |
| 1989 | Protection and Versioning for OCT. Mário J. Silva, David Gedye, Randy H. Katz, Richard Newton |
| 1989 | REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man |
| 1989 | Representation and Use of Design Rules within a Technology Adaptable CAD System. Júlio S. Aude, Hilary J. Kahn |
| 1989 | Resistance Extraction and Resistance Calculation in GOALIE? Kuang-Wei Chiang |
| 1989 | Rule-based VLSI Verification System Constrained by Layout Parasitics. Jacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels |
| 1989 | Scheduling High-Level Blocks for Functional Simulation. Zhicheng Wang, Peter M. Maurer |
| 1989 | Scheduling and Binding Algorithms for High-Level Synthesis. Pierre G. Paulin, John P. Knight |
| 1989 | Semantics of a Hardware Design Language for Japanese Standardization. Hiroto Yasuura, Nagisa Ishiura |
| 1989 | Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. Ran Libeskind-Hadas, C. L. Liu |
| 1989 | Special Purpose Architecture for Accelerating Bitmap DRC. Narasimha B. Bhat, S. K. Nandy |
| 1989 | State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. Gabriele Saucier, Christopher Duff, Franck Poirot |
| 1989 | Static Timing Analysis of Dynamically Sensitizable Paths. S. Perremans, Luc J. M. Claesen, Hugo De Man |
| 1989 | Technology Tracking of Non Manhattan VLSI Layout. Johannes Waterkamp, Ralner Wicke, Rainer Brück, Michael Reinhardt, Georg Schrammeck |
| 1989 | Template Style Considerations for Sea-of-Gates Layout Generation. G. D. Adams, Carlo H. Séquin |
| 1989 | Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim |
| 1989 | Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation. Kyeongsoon Cho, Randal E. Bryant |
| 1989 | The Layout Synthesizer: An Automatic Netlist-to-Layout System. C. C. Chen, S.-L. Chow |
| 1989 | The MICON System for Computer Design. William P. Birmingham, Anurag P. Gupta, Daniel P. Siewiorek |
| 1989 | The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment. Julia Miller, Klaus Gröning, Gerhard Schulz, Charles White |
| 1989 | The Social Implications of Computerization: Making the Technology Humane. Michael C. McFarland |
| 1989 | The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. Nils Hedenstierna, Kjell O. Jeppson |
| 1989 | Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. Kurt Keutzer |
| 1989 | Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima |
| 1989 | Timing Analysis in a Logic Synthesis Environment. Nicholas Weiner, Alberto L. Sangiovanni-Vincentelli |
| 1989 | Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. Jacques Benkoski, Andrzej J. Strojwas |
| 1989 | Toward Synthesis from English Descriptions. Walling R. Cyre |
| 1989 | Transistor Size Optimization in the Tailor Layout System. David Marple |
| 1989 | Use of Change Coordination in an Information-rich Design Environment. Marianne Winslett, David W. Knapp, Keith Hall, Gio Wiederhold |
| 1989 | VHDL Synthesis Using Structured Modeling. Joseph Lis, Daniel Gajski |
| 1989 | VIA Minimization by Layout Modification. Khe-Sing The, D. F. Wong, Jason Cong |
| 1989 | VLSI Design Language Standardization Effort in Japan. Osamu Karatsu |
| 1989 | VVDS: A Verification/Diagnosis System for VHDL. Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin |
| 1989 | Verification of Hardware Descriptions by Retargetable Code Generation. Lothar Nowak, Peter Marwedel |
| 1989 | Worst-case Delay Estimation of Transistor Groups. Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin |
| 1989 | iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development. Andrew T. Yang, S. M. Kang |