DAC A*

129 papers

YearTitle / Authors
1987"?": A Context-Sensitive Help System Based on Hypertext.
William Lee
1987A "gridless" Variable-Width Channel Router for Marco Cell Design.
Charles H. Ng
1987A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator.
Norman J. Elias
1987A Conceptual Framework for Designing ASIC Hardware.
Steven S. Leung, Michael A. Shanblatt
1987A Design Rule Independent Cell Compiler.
John S. J. Chen, David Y. Chen
1987A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts.
Ali A. Minai, Ronald D. Williams, F. W. Blake
1987A Dynamic Programming Approach to the Test Point Insertion Problem.
Balakrishnan Krishnamurthy
1987A Dynamic and Efficient Representation of Building-Block Layout.
Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh
1987A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.
S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter
1987A Hardware Accelerator for Maze Routing.
Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq
1987A Hardware Switch Level Simulator for Large MOS Circuits.
M. T. Smith
1987A Hierarchical Approach Test Vector Generation.
Susheel J. Chandra, Janak H. Patel
1987A High Performance Routing Engine.
T. D. Spiers, D. A. Edwards
1987A New Compaction Scheme Based on Compression Ridges.
P. C. Shah, Hosaker N. Mahabala
1987A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards.
Eric Rosenberg
1987A Parallel PLA Minimization Program.
R. Galivanche, Sudhakar M. Reddy
1987A Parts Selection Expert System to Increase Manufacturability.
D. Praizler, G. Fritz
1987A Path Selection Global Router.
Y. C. Hsu, Y. Pan, William J. Kubitz
1987A Practical Moat Router.
R. K. McGehee
1987A Preliminary Investigation into Parallel Routing on a Hypercube Computer.
Kunle Olukotun, Trevor N. Mudge
1987A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1987A Rule-Based Circuit Representation for Automated CMOS Design and Verification.
Ching-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni
1987A Rule-Based Placement System for Printed Wiring Boards.
Gotaro Odawara, T. Hamuro, Kazuhiko Iijima, T. Yoshino, Y. Dai
1987A Three-Layer Gridless Channel Router with Compaction.
D. B. Polkl
1987A Topological Search Algorithm for ATPG.
Tom E. Kirkland, M. Ray Mercer
1987A Vector Hardware Accelerator with Circuit Simulation Emphasis.
Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass
1987ASTA: LSI Design Management System.
Takuji Ogihara, Hiromi Toyoshima, Shinichi Murai
1987Abstract Routing of Logic Networks for Custom Module Generation.
Steven T. Healey, William J. Kubitz
1987Accelerated Transition Fault Simulation.
Michael H. Schultz, Franc Brglez
1987Aesop: A Tool for Automated Transistor Sizing.
Kye S. Hedlund
1987An Application of Exploratory Data Analysis Techniques to Floorplan Design.
E. F. M. Kouka, Gabriele Saucier
1987An Automated Design of Minimum-Area IC Power/Ground Nets.
S. Chowdhury
1987An Automatic Rectilinear Partitioning Procedure for Standard Cells.
Mely Chen Chi
1987An Expert System Application in Semicustom VLSI Design.
Robin L. Steele
1987An Improved Systematic Method for Constructing Systolic Arrays from Algorithms.
Nikrouz Faroughi, Michael A. Shanblatt
1987An Intelligent Compiler Subsystem for a Silicon Compiler.
D. L. Johannsen, S. K. Tsubota, Kenneth S. McElvain
1987An Interface between VHDL and EDIF.
Moe Shahdad
1987An Object-Oriented Approach to Data Management: Why Design Databases Need It.
Sandra Heiler, Umeshwar Dayal, Jack A. Orenstein, Susan Radke-Sproull
1987An Overview of Logic Synthesis Systems.
Louise Trevillyan
1987An Overview of the Penn State Design System.
Robert Michael Owens, Mary Jane Irwin
1987Application of Term Rewriting Techniques to Hardware Design Verification.
Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt
1987Architecture and Design of the MARS Hardware Accelerator.
Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar
1987Array Optimization for VLSI Synthesis.
D. F. Wong, C. L. Liu
1987Automated Layout Generation Using Gate Matrix Approach.
Y.-C. Chang, S. C. Chang, L.-H. Hsu
1987BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.
Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya
1987Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits.
M. Ladjadj, John F. McDonald
1987Benchmarks for Cell-Based Layout Systems.
Bryan Preas
1987Boolean Comparison by Simulation.
Edward P. Stabler, Haluk Bingol
1987CASE: An Integrated Design Environment for Algorithm-Driven Architectures.
Dick C. A. Bulterman
1987CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools.
Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny
1987COSMOS: A Compiled Simulator for MOS Circuits.
Randal E. Bryant, Derek L. Beatty, Karl S. Brace, Kyeongsoon Cho, Thomas J. Sheffler
1987Circuit Simulation on the Connection Machine.
Donald M. Webber, Alberto L. Sangiovanni-Vincentelli
1987Circular Self-Test Path: A Low-Cost BIST Technique.
Andrzej Krasniewski, Slawomir Pilarski
1987DAGON: Technology Binding and Local Optimization by DAG Matching.
Kurt Keutzer
1987Delay Optimization of Combinational Static CMOS Logic.
Mark Hofmann, Jae K. Kim
1987Demand Driven Simulation: BACKSIM.
Steven P. Smith, M. Ray Mercer, B. Brodk
1987Design Automation Standards - Perspectives from a Down-the-Road End User.
Roger J. Pachter
1987Design Automation Standards Need Integration.
L. O'Connell
1987Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories.
Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
1987EASE: A Design Support Environment for the HDDL ELLA.
J. D. Morison, N. E. Peeling, T. L. Thorp, E. V. Whiting
1987ESP: A New Standard Cell Placement Package Using Simulated Evolution.
Ralph-Michael Kling, Prithviraj Banerjee
1987Fast Printed Circuit Board Routing.
Jeremy Dion
1987Fast, Small, and Static Combinatorial CMOS Circuits.
Bertrand Serlet
1987Faster Architectural Simulation Through Parallelism.
J. W. Smith, K. S. Smith, Robert J. Smith
1987Finding the Optimal Variable Ordering for Binary Decision Diagrams.
Steven J. Friedman, Kenneth J. Supowit
1987Force-Directed Scheduling in Automatic Data Path Synthesis.
Pierre G. Paulin, John P. Knight
1987Function Search from Behavioral Description of a Digital System.
Jung-Gen Wu, William P.-C. Ho, Yu Hen Hu, David Y. Y. Yun, H. J. Yu
1987Functional Abstraction from Structure in VLSI Simulation Models.
Richard H. Lathrop, Robert J. Hall, Robert S. Kirk
1987Functional Verification of MOS Circuits.
Daniel Weise
1987General Purpose Router.
Richard J. Enbody, Hung-Chang Du
1987Generating Incremental VLSI Compaction Spacing Constraints.
Clyde W. Carpenter, Mark Horowitz
1987Geometrical Compaction in One Dimension for Channel Routing.
J. Royle, Mikael Palczewski, H. VerHeyen, N. Naccache, Jiri Soukup
1987HPEX: A Hierarchical Parasitic Circuit Extractor.
Shun-Lin Su, Vasant B. Rao, Timothy N. Trick
1987Heuristic Acceleration of Force-Directed Placement.
R. Forbes
1987Hierarchical Design Based on a Calculus of Nets.
Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof
1987Improving Virtual-Grid Compaction Through Grouping.
Lars S. Nyland, Stephen W. Daniel, C. Durward Rogers
1987Improving a PLA Area by Pull-Up Transistor Folding.
Chidchanok Lursinsap, Daniel Gajski
1987Integrating Design Information for IC Diagnosis.
S. E. Concina, G. S. Liu
1987KAHLUA: A Hierarchical Circuit Disassembler.
Bill Lin, A. Richard Newton
1987Knowledge Based Approach for the Verification of CAD Database Generated by an Automated Schematic Capture System.
J. Y. Tou, W. H. Ki, K. C. Fan, C. L. Huang
1987Knowledge Based Control in Micro-Architecture Design.
Forrest Brewer, Daniel Gajski
1987LCS - A Leaf Cell Synthesizer Employing Formal Deduction Techniques.
P. A. Subrahmanyam
1987LES: A Layout Expert System.
Youn-Long Lin, Daniel Gajski
1987Layout Optimization of CMOS Functional Cells.
R. L. Maiasz, John P. Hayes
1987Logic Verification Algorithms and Their Parallel Implementation.
Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, Ruey-Sing Wei
1987Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation.
Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin
1987Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms.
M. L. Brei
1987Nutcracker: An Efficient and Intelligent Channel Spacer.
Xiao-Ming Xiong, Ernest S. Kuh
1987On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates.
Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana
1987On Computing Optimized Input Probabilities for Random Tests.
Hans-Joachim Wunderlich
1987On Yield Consideration for the Design of Redundant Programmable Logic Arrays.
Chin-Long Wey
1987On the Verification of Sequential Machines at Differing Levels of Abstraction.
Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1987Optimal Layout to Avoid CMOS Stuck-Open Faults.
S. Koeppe
1987PALMINI - Fast Boolean Minimizer for Personal Computers.
L. B. Nguyen, M. A. Perkowdki, N. B. Goldstein
1987PAMS: An Expert System for Parameterized Module Synthesis.
T. Cesear, E. Iodice, C. Tsareff
1987PHRAN-SPAN: A Natural Language Interface for System Specifications.
John J. Granacki Jr., Alice C. Parker
1987PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement.
Wen-Jeng Lue, Lawrence P. McNamee
1987Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube.
Mark Jones, Prithviraj Banerjee
1987Predicting Area-Time Tradeoffs for Pipelined Design.
Rajiv Jain, Alice C. Parker, Nohbyung Park
1987Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987.
A. O'Neill, D. Thomas
1987Querying Part Hierarchies: A Knowledge-Based Approach.
Arnon Rosenthal, Sandra Heiler
1987REAL: a program for REgister ALlocation.
Fadi J. Kurdahi, Alice C. Parker
1987RED: Resistance Extraction for Digital Simulation.
Don Stark, Mark Horowitz
1987Rational for and Organization of the Engineering Information System Program.
Anthony J. Gadient, J. L. Ebel
1987Realistic Fault Modeling for VLSI Testing.
Wojciech Maly
1987Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic.
Robert E. Canright, A. R. Helland
1987Requirements for a Practical Software Engineering Environment.
V. Masurkar
1987Routing L-Shaped Channels in Nonslicing-Structure Placement.
H. H. Chen
1987Routing with a Scanning Window-8Ma Unified Approach.
David Kaplan
1987SSIM: A Software Levelized Compiled-Code Simulator.
L.-T. Wang, Nathan E. Hoover, Edwin H. Porter, John J. Zasio
1987STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct.
Emil F. Girczyc, Tai A. Ly
1987Standard Cell Placement Using Simulated Sintering.
Lov K. Grover
1987Statistics for Parallelism and Abstraction Level in Digital Simulation.
Larry Soulé, R. Blank
1987Strip Layout: A New Layout Methodology for Standard Circuit Modules.
J. Apte, Gershon Kedem
1987Switch Directed Dynamic Causal Networks - a Paradigm for Electronic System Diagnosis.
Robert M. McDermott, David Stern
1987TED: A Graphical Technology Description Editor.
William Lee, Gerald Liu, Kevin Peterson
1987TRIP: An Automated Technology Mapping System.
Shigenobu Suzuki, Tatsushige Bitoh, Masao Kakimoto, Kazutoshi Takahashi, Takao Sugimoto
1987The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.
Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp
1987The Design Automation Standards Environment.
Ronald Waxman
1987The IBM VHDL Design System.
Larry F. Saunders
1987The Implementation of a State Machine Compiler.
Christopher Kingsley
1987The Making of VIVID: A Software Engineering Perspective.
Jonathan B. Rosenberg
1987Transistor Sizing in CMOS Circuits.
Mehmet A. Cirit
1987Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis.
Curtis H. Parks
1987VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data.
Rajiv Bhateja, Randy H. Katz
1987VISION: VHDL Induced Schematic Imaging on Net-Lists.
Robert K. Chun, Keh-Jeng Chang, Lawrence P. McNamee
1987VLSI Circuit Testing Using an Adaptive Optimization Model.
Philip S. Yu, C. Mani Krishna, Yann-Hang Lee
1987Via Minimization for Gridless Layouts.
Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima
1987Where VHDL Fits Within the CAD Environment.
J. Hines