DAC A*

194 papers

YearTitle / Authors
2009A DVS-based pipelined reconfigurable instruction memory.
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
2009A Gaussian mixture model for statistical timing analysis.
Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama
2009A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems.
Yuan-Hao Chang, Tei-Wei Kuo
2009A computing origami: folding streams in FPGAs.
Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah
2009A correct network flow model for escape routing.
Tan Yan, Martin D. F. Wong
2009A design flow for application specific heterogeneous pipelined multiprocessor systems.
Haris Javaid, Sri Parameswaran
2009A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction.
Wenwen Chai, Dan Jiao, Cheng-Kok Koh
2009A false-path aware formal static timing analyzer considering simultaneous input transitions.
Shihheng Tsai, Chung-Yang Huang
2009A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.
Shiyan Hu, Zhuo Li, Charles J. Alpert
2009A learning digital computer.
Bo Marr, Arindam Basu, Stephen Brink, Paul E. Hasler
2009A moment-based effective characterization waveform for static timing analysis.
David D. Ling, Chandu Visweswariah, Peter Feldmann, Soroush Abbaspour
2009A novel verification technique to uncover out-of-order DUV behaviors.
Gabriel Marcilio, Luiz C. V. dos Santos, Bruno C. Albertini, Sandro Rigo
2009A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management.
Hamid Shojaei, Amir Hossein Ghamarian, Twan Basten, Marc Geilen, Sander Stuijk, Rob Hoes
2009A parameterized mask model for lithography simulation.
Zhenhai Zhu
2009A parametric approach for handling local variation effects in timing analysis.
Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik
2009A physical unclonable function defined using power distribution system equivalent resistance variations.
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
2009A real-time program trace compressor utilizing double move-to-front method.
Vladimir Uzelac, Aleksandar Milenkovic
2009A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian.
Amit Mehrotra, Abhishek Somani
2009A stochastic jitter model for analyzing digital timing-recovery circuits.
James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi
2009A trace-capable instruction cache for cost efficient real-time program trace compression in SoC.
Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang
2009A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2009ARMS - automatic residue-minimization based sampling for multi-point modeling techniques.
Jorge Fernandez Villena, Luís Miguel Silveira
2009Accurate temperature estimation using noisy thermal sensors.
Yufu Zhang, Ankur Srivastava
2009ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models.
Cedric Walravens, Yves Vanderperren, Wim Dehaene
2009Adaptive test elimination for analog/RF circuits.
Ender Yilmaz, Sule Ozev
2009Addressing design margins through error-tolerant circuits.
Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken
2009An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction.
Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Yao-Hsin Chou
2009An SDRAM-aware router for Networks-on-Chip.
Wooyoung Jang, David Z. Pan
2009An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems.
Shaobo Liu, Qing Wu, Qinru Qiu
2009An efficient approach for system-level timing simulation of compiler-optimized embedded software.
Zhonglei Wang, Andreas Herkersdorf
2009An efficient passivity test for descriptor systems via canonical projector techniques.
Ngai Wong
2009An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes.
Tarek A. El-Moselhy, Ibrahim M. Elfadel, Bill Dewey
2009Analysis and mitigation of process variation impacts on Power-Attack Tolerance.
Lang Lin, Wayne P. Burleson
2009Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.
Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha
2009Automated failure population creation for validating integrated circuit diagnosis methods.
Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
2009Automatic bus planner for dense PCBs.
Hui Kong, Tan Yan, Martin D. F. Wong
2009BDD-based synthesis of reversible logic for large functions.
Robert Wille, Rolf Drechsler
2009Beyond innovation: dealing with the risks and complexity of processor design in 22nm.
Carl J. Anderson
2009Beyond verification: leveraging formal for debugging.
Rajeev K. Ranjan, Claudionor Coelho, Sebastian Skalberg
2009Boolean logic function synthesis for generalised threshold gate circuits.
Marek A. Bawiec, Maciej Nikodem
2009CMOS scaling beyond 32nm: challenges and opportunities.
Kelin J. Kuhn
2009Carbon nanotube circuits in the presence of carbon nanotube density variations.
Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra
2009Circuit techniques for dynamic variation tolerance.
Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
2009Clock skew optimization via wiresizing for timing sign-off covering all process corners.
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
2009Computing bounds for fault tolerance using formal techniques.
Görschwin Fey, André Sülflow, Rolf Drechsler
2009Constraints in one-to-many concretization for abstraction refinement.
Kuntal Nanshi, Fabio Somenzi
2009Context-sensitive timing analysis of Esterel programs.
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury
2009Contract-based system-level composition of analog circuits.
Xuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli
2009Creating an affordable 22nm node using design-lithography co-optimization.
Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
2009DFM: don't care or competitive weapon?
Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels
2009Debugging from high level down to gate level.
Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi
2009Debugging strategies for mere mortals.
Valeria Bertacco
2009Decoding nanowire arrays fabricated with the multi-spacer patterning technique.
M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli
2009Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study.
Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon
2009Design perspectives on 22nm CMOS and beyond.
Shekhar Borkar
2009Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis.
Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty
2009Device/circuit interactions at 22nm technology node.
Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta
2009Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
2009Double patterning lithography friendly detailed routing with redundant via consideration.
Kun Yuan, Katrina Lu, David Z. Pan
2009Dynamic thermal management via architectural adaptation.
Ramkumar Jayaseelan, Tulika Mitra
2009Dynamic thread and data mapping for NoC based CMPs.
Mahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara
2009EDA in flux: should I stay or should I go?
Eshel Haritan, Andreas Kuehlmann, Tina Jones, John Epperheimer, Jan M. Rabaey, Rahul Razdan, Naveen Gupta
2009Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts.
Himanshu Jain, Edmund M. Clarke
2009Efficient design-specific worst-case corner extraction for integrated circuits.
Hong Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li
2009Efficient program scheduling for heterogeneous multi-core processors.
Jian Chen, Lizy Kurian John
2009Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.
Vineeth Veetil, Dennis Sylvester, David T. Blaauw, Saumil Shah, Steffen Rochel
2009Enabling adaptability through elastic clocks.
Emre Tuncer, Jordi Cortadella, Luciano Lavagno
2009Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity.
Pai H. Chou
2009Energy-aware error control coding for Flash memories.
Veera Papirla, Chaitali Chakrabarti
2009Evaluating design trade-offs in customizable processors.
Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra
2009Event-driven gate-level simulation with GP-GPUs.
Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
2009Exploiting "architecture for verification" to streamline the verification process.
Dave Whipp
2009Exploring serial vertical interconnects for 3D ICs.
Sudeep Pasricha
2009FPGA-based accelerator for the verification of leading-edge wireless systems.
Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn
2009FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.
Scott Cromar, Jaeho Lee, Deming Chen
2009Fast vectorless power grid verification using an approximate inverse technique.
Nahi H. Abdul Ghani, Farid N. Najm
2009Fault models for embedded-DRAM macros.
Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin
2009Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression.
Xin Li
2009Flip-chip routing with unified area-I/O pad assignments for package-board co-design.
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
2009From milliwatts to megawatts: system level power challenge.
Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach
2009GPU friendly fast Poisson solver for structured power grid network analysis.
Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang
2009GPU-based parallelization for fast circuit optimization.
Yifang Liu, Jiang Hu
2009GRIP: scalable 3D global routing using integer programming.
Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2009Generating test programs to cover pipeline interactions.
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra
2009Green data centers and hot chips.
Dilip D. Kandlur, Tom W. Keller
2009Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong
2009Handling complexities in modern large-scale mixed-size placement.
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
2009Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2009Hardware Trojan horse detection using gate-level characterization.
Miodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey
2009Hardware authentication leveraging performance limits in detailed simulations and emulations.
Daniel Y. Deng, Andrew H. Chan, G. Edward Suh
2009Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators.
José Baiocchi, Bruce R. Childers
2009Hierarchical architecture of flash-based storage systems for high performance and durability.
Sanghyuk Jung, Jin Hyuk Kim, Yong Ho Song
2009Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.
Yoonjin Kim, Rabi N. Mahapatra
2009Holistic verification: myth or magic bullet?
Pradip A. Thaker
2009How to make computers that work like the brain.
Dileep George
2009Human computation.
Luis von Ahn
2009Human computing for EDA.
Andrew DeOrio, Valeria Bertacco
2009ILP-based pin-count aware design methodology for microfluidic biochips.
Cliff Chiung-Yu Lin, Yao-Wen Chang
2009Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
2009Improving testability and soft-error resilience through retiming.
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2009Information hiding for trusted system design.
Junjun Gu, Gang Qu, Qiang Zhou
2009Interconnection fabric design for tracing signals in post-silicon validation.
Xiao Liu, Qiang Xu
2009Internet-in-a-Box: emulating datacenter network architectures using FPGAs.
Jonathan D. Ellithorpe, Zhangxi Tan, Randy H. Katz
2009LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.
Talal Bonny, Jörg Henkel
2009Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
2009MAGENTA: transaction-based statistical micro-architectural root-cause analysis.
Gila Kamhi, Alexander Novakovsky, Andreas Tiemeyer, Adriana Wolffberg
2009MPTLsim: a simulator for X86 multicore processors.
Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev
2009Massively parallel processing: it's déjà vu all over again.
Steven P. Levitan, Donald M. Chiarulli
2009Matching-based minimum-cost spare cell selection for design changes.
Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung
2009Misleading performance claims in parallel computations.
David H. Bailey
2009Mode grouping for more effective generalized scheduling of dynamic dataflow applications.
William Plishker, Nimish Sane, Shuvra S. Bhattacharyya
2009Moore's Law: another casualty of the financial meltdown?
Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork
2009Multicore parallel min-cost flow algorithm for CAD applications.
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
2009Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency.
Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi
2009NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core.
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su
2009Nanoscale digital computation through percolation.
Mustafa Altun, Marc D. Riedel, Claudia Neuhauser
2009New spare cell design for IR drop minimization in Engineering Change Order.
Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang
2009No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang
2009NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2009Non-cycle-accurate sequential equivalence checking.
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma
2009Non-intrusive dynamic application profiling for multitasked applications.
Karthik Shankar, Roman L. Lysecky
2009O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration.
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan
2009Oil fields, hedge funds, and drugs.
Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen
2009On systematic illegal state identification for pseudo-functional testing.
Feng Yuan, Qiang Xu
2009On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration.
Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng
2009Online cache state dumping for processor debug.
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
2009Optimal static WCET-aware scratchpad allocation of program code.
Heiko Falk, Jan C. Kleinsorge
2009Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.
Jungseob Lee, Nam Sung Kim
2009Optimum LDPC decoder: a memory architecture problem.
Erick Amador, Renaud Pacalet, Vincent Rezard
2009PDRAM: a hybrid PRAM and DRAM main memory system.
Gaurav Dhiman, Raid Zuhair Ayoub, Tajana Rosing
2009Parallelizable stable explicit numerical integration for efficient circuit simulation.
Wei Dong, Peng Li
2009Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.
Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He
2009PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.
Fang Gong, Hao Yu, Lei He
2009Polynomial datapath optimization using partitioning and compensation heuristics.
Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
2009Power modeling of graphical user interfaces on OLED displays.
Mian Dong, Yung-Seok Kevin Choi, Lin Zhong
2009Predicting variability in nanoscale lithography processes.
Dragoljub Gagi Drmanac, Frank Liu, Li-C. Wang
2009Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009
2009Process variation characterization of chip-level multiprocessors.
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph
2009Programmable neural processing on a smartdust.
Shimeng Huang, Joseph Oresko, Yuwen Sun, Allen C. Cheng
2009Provably good and practically efficient algorithms for CMP dummy fill.
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2009Quality-driven synthesis of embedded multi-mode control systems.
Soheil Samii, Petru Eles, Zebo Peng, Anton Cervin
2009Reduction techniques for synchronous dataflow graphs.
Marc Geilen
2009RegPlace: a high quality open-source placement framework for structured ASICs.
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
2009Register allocation for high-level synthesis using dual supply voltages.
Insup Shin, Seungwhun Paik, Youngsoo Shin
2009Regression verification.
Benny Godlin, Ofer Strichman
2009Resurrecting infeasible clock-gating functions.
Eli Arbel, Cindy Eisner, Oleg Rokhlenko
2009Retiming and recycling for elastic systems with early evaluation.
Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky
2009Role of the verification team throughout the ASIC development life cycle.
Eric Chesters
2009SRAM parametric failure analysis.
Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi
2009Scheduling the FlexRay bus using optimization techniques.
Haibo Zeng, Wei Zheng, Marco Di Natale, Arkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli
2009Selective wordline voltage boosting for caches to manage yield under process variations.
Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung
2009Serial reconfigurable mismatch-tolerant clock distribution.
Atanu Chattopadhyay, Zeljko Zilic
2009Shortening the verification cycle with synthesizable abstract models.
Alon Gluska, Lior Libis
2009Simulation and SAT-based Boolean matching for large Boolean networks.
Kuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu
2009Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
Hochang Jang, Taewhan Kim
2009Single-electron devices for ubiquitous and secure computing applications.
Ken Uchida
2009Soft connections: addressing the hardware-design modularity problem.
Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer
2009Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.
Weiguang Sheng, Liyi Xiao, Zhigang Mao
2009Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks
2009Spare-cell-aware multilevel analytical placement.
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao
2009Spectral techniques for high-resolution thermal characterization with limited sensor data.
Ryan Cochran, Sherief Reda
2009Spectrum: a hybrid nanophotonic-electric on-chip network.
Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
2009Speculation in elastic systems.
Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky
2009Speedpath analysis based on hypothesis pruning and ranking.
Nicholas Callegari, Li-C. Wang, Pouria Bastani
2009Statistical multilayer process space coverage for at-speed test.
Jinjun Xiong, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah
2009Statistical ordering of correlated timing quantities and its application for path ranking.
Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov
2009Statistical reliability analysis under process variation and aging effects.
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng
2009Stochastic steady-state and AC analyses of mixed-signal systems.
Jaeha Kim, Jihong Ren, Mark A. Horowitz
2009Sustainable data centers: enabled by supply and demand side management.
Prith Banerjee, Chandrakant D. Patel, Cullen E. Bash, Parthasarathy Ranganathan
2009Synthesizing hardware from sketches.
Andreas Raabe, Rastislav Bodík
2009SysCOLA: a framework for co-development of automotive software and system platform.
Zhonglei Wang, Andreas Herkersdorf, Wolfgang Haberl, Martin Wechs
2009System prototypes: virtual, hardware or hybrid?
Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl
2009Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective.
Siddharth Garg, Diana Marculescu, Radu Marculescu, Ümit Y. Ogras
2009The Cilk++ concurrency platform.
Charles E. Leiserson
2009The day Sherlock Holmes decided to do EDA.
Andreas G. Veneris, Sean Safarpour
2009The semiconductor industry's nanoelectronics research initiative: motivation and challenges.
Jeff Welser
2009The wild west: conquest of complex hardware-dependent software design.
Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti
2009Thermal-aware data flow analysis.
José Luis Ayala, David Atienza, Philip Brisk
2009Thermal-driven analog placement considering device matching.
Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2009Throughput optimal task allocation under thermal constraints for multi-core processors.
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
2009Timing-driven optimization using lookahead logic circuits.
Mihir R. Choudhury, Kartik Mohanram
2009Trace-driven workload simulation method for Multiprocessor System-On-Chips.
Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou
2009Transmuting coprocessors: dynamic loading of FPGA coprocessors.
Chen Huang, Frank Vahid
2009Untwist your brain: efficient debugging and diagnosis of complex assertions.
Michael Siegel, Adriana Maggiore, Christian Pichler
2009Use of lithography simulation for the calibration of equation-based design rule checks.
David Abercrombie, Fedor Pikus, Cosmin Cazan
2009Variability analysis under layout pattern-dependent rapid-thermal annealing process.
Yun Ye, Frank Liu, Min Chen, Yu Cao
2009Variational capacitance extraction of on-chip interconnects based on continuous surface model.
Wenjian Yu, Chao Hu, Wangyang Zhang
2009Verification problems in reusing internal design components.
Warren Stapleton, Paul Tobin
2009Vicis: a reliable network for unreliable silicon.
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester
2009WCET-aware register allocation based on graph coloring.
Heiko Falk
2009Way Stealing: cache-assisted automatic instruction set extensions.
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
2009Worst-case aggressor-victim alignment with current-source driver models.
Ravikishore Gandikota, Li Ding, Peivand Tehrani, David T. Blaauw
2009Xquasher: a tool for efficient computation of multiple linear expressions.
Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner
2009Yield-driven iterative robust circuit optimization algorithm.
Yan Li, Vladimir Stojanovic