DAC A*

196 papers

YearTitle / Authors
2008(Bio)-behavioral CAD.
Miodrag Potkonjak, Farinaz Koushanfar
20083-D semiconductor's: more from Moore.
Ted Vucurevich
2008A "true" electrical cell model for timing, noise, and power grid verification.
Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin
2008A 242mW, 10mm
Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang
2008A MIPS R2000 implementation.
Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips
2008A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.
Ming-Che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai
2008A fast, analytical estimator for the SEU-induced pulse width in combinational designs.
Rajesh Garg, Charu Nagpal, Sunil P. Khatri
2008A framework for block-based timing sensitivity analysis.
Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar
2008A generalized network flow based algorithm for power-aware FPGA memory mapping.
Tien-Yuan Hsu, Ting-Chi Wang
2008A methodology for statistical estimation of read access yield in SRAMs.
Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis
2008A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer.
Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang
2008A new paradigm for synthesis and propagation of clock gating conditions.
Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed
2008A power and temperature aware DRAM architecture.
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik
2008A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.
Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo
2008A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.
John D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang
2008A progressive-ILP based routing algorithm for cross-referencing biochips.
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2008A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.
Zhen Zhang, Alain Greiner, Sami Taktak
2008ADAM: run-time agent-based distributed application mapping for on-chip communication.
Mohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel
2008Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications.
Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen
2008Addressing library creation challenges from recent Liberty extensions.
Richard Trihy
2008An 8x8 run-time reconfigurable FPGA embedded in a SoC.
Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger
2008An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing.
Aydin O. Balkan, Gang Qu, Uzi Vishkin
2008An automatic scratch pad memory management tool and MPEG-4 encoder case study.
Rogier Baert, Eddy de Greef, Erik Brockmeyer
2008An efficient incremental algorithm for min-area retiming.
Jia Wang, Hai Zhou
2008An embedded infrastructure of debug and trace interface for the DSP platform.
Ming-Chang Hsieh, Chih-Tsun Huang
2008An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
2008Analog parallelism in ring-based VCOs.
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
2008Analog placement based on hierarchical module clustering.
Mark Po-Hung Lin, Shyh-Chang Lin
2008Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs.
Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee
2008Application mapping for chip multiprocessors.
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. Kandemir
2008Application-driven floorplan-aware voltage island design.
Dipanjan Sengupta, Resve A. Saleh
2008Applying passive RFID system to wireless headphones for extreme low power consumption.
Joon Goo Lee, Dongha Jung, Jiho Chu, Seokjoong Hwang, Jong-Kook Kim, Janam Ku, Seon Wook Kim
2008Assertion-based verification of a 32 thread SPARC
Babu Turumella, Mukesh Sharma
2008Automated design of self-adjusting pipelines.
Jieyi Long, Seda Ogrenci Memik
2008Automated design of tunable impedance matching networks for reconfigurable wireless applications.
Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud
2008Automated hardware-independent scenario identification.
Juan Hamers, Lieven Eeckhout
2008Automated transistor sizing for FPGA architecture exploration.
Ian Kuon, Jonathan Rose
2008Automatic architecture refinement techniques for customizing processing elements.
Bita Gorjiara, Daniel Gajski
2008Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM.
Krishna Bharath, Ege Engin, Madhavan Swaminathan
2008Automatic synthesis of clock gating logic with controlled netlist perturbation.
Aaron P. Hurst
2008Bi-decomposing large Boolean functions via interpolation and satisfiability solving.
Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung
2008Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.
Hazem Moussa, Amer Baghdadi, Michel Jézéquel
2008Bounded-lifetime integrated circuits.
Puneet Gupta, Andrew B. Kahng
2008Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips.
Tao Xu, Krishnendu Chakrabarty
2008C-based design flow: a case study on G.729A for voice over internet protocol (VoIP).
Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski
2008Cache modeling in probabilistic execution time analysis.
Yun Liang, Tulika Mitra
2008Challenges in gate level modeling for delay and SI at 65nm and below.
Igor Keller, King Ho Tam, Vinod Kariat
2008Challenges in using system-level models for RTL verification.
Kelvin Ng
2008Characterizing chip-multiprocessor variability-tolerance.
Sebastian Herbert, Diana Marculescu
2008Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen
2008Circuit-wise buffer insertion and gate sizing algorithm with scalability.
Zhanyuan Jiang, Weiping Shi
2008Collective computing based on swarm intelligence.
Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
2008Compiler-driven register re-assignment for register file power-density and temperature reduction.
Xiangrong Zhou, Chenjie Yu, Peter Petrov
2008Compositional verification of retiming and sequential optimizations.
In-Ho Moon
2008Concurrent topology and routing optimization in automotive network integration.
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang
2008Construction of concrete verification models from C++.
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh
2008Control theory-based DVS for interactive 3D games.
Yan Gu, Samarjit Chakraborty
2008Custom is from Venus and synthesis from Mars.
Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye
2008Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.
Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao
2008DFM in practice: hit or hype?
Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh
2008DVFS in loop accelerators using BLADES.
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull
2008Daedalus: toward composable multimedia MP-SoC design.
Hristo Nikolov, Mark Thompson, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere
2008DeFer: deferred decision making enabled fixed-outline floorplanner.
Jackey Z. Yan, Chris Chu
2008DeMOR: decentralized model order reduction of linear networks with massive ports.
Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy
2008Design and CAD for 3D integrated circuits.
Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller
2008Design of a mask-programmable memory/multiplier array using G4-FET technology.
Jay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi
2008Design of high performance pattern matching engine through compact deterministic finite automata.
Piti Piyachon, Yan Luo
2008Design-process integration for performance-based OPC framework.
Siew-Hong Teh, Chun-Huat Heng, Arthur Tay
2008Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2008Driver waveform computation for timing analysis with multiple voltage threshold driver models.
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta
2008Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum
2008ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
2008ESL hand-off: fact or EDA fiction?
Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini
2008ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.
Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
2008Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic.
C. Richard Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw
2008Efficient Monte Carlo based incremental statistical timing analysis.
Vineeth Veetil, Dennis Sylvester, David T. Blaauw
2008Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters.
Tarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger
2008Efficient system design space exploration using machine learning techniques.
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary
2008Election year: what the electronics industry needs---and can expect---from the incoming administration.
Tiffany Sparks, Pete Weitzner, Luc Burgun, Russell Lefevre, Todd Cutler, Clayton Parker, Vicki Hadfield, Chris Rowen
2008Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects.
Ki Jin Han, Madhavan Swaminathan, Ege Engin
2008Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems.
Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos, Slobodan Matic, Bodhi Priyantha, Feng Zhao
2008Enhancing timing-driven FPGA placement for pipelined netlists.
Kenneth Eguro, Scott Hauck
2008Exploring locking & partitioning for predictable shared caches on multi-cores.
Vivy Suhendra, Tulika Mitra
2008FPGA area reduction by multi-output function based sequential resynthesis.
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2008Faster symmetry discovery using sparsity of symmetries.
Paul T. Darga, Karem A. Sakallah, Igor L. Markov
2008Federation: repurposing scalar cores for out-of-order instruction issue.
David Tarjan, Michael Boyer, Kevin Skadron
2008Feedback-controlled reliability-aware power management for real-time embedded systems.
Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra
2008Flow engineering for physical implementation: theory and practice.
Steve Golson, Pete Churchill
2008Forbidden transition free crosstalk avoidance CODEC design.
Chunjie Duan, Chengyu Zhu, Sunil P. Khatri
2008Formal datapath representation and manipulation for implementing DSP transforms.
Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel
2008Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification.
Tao Li, Wenjun Zhang, Zhiping Yu
2008Functional test selection based on unsupervised support vector analysis.
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster
2008Functionally linear decomposition and synthesis of logic circuits for FPGAs.
Tomasz S. Czajkowski, Stephen Dean Brown
2008Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis.
Zuochang Ye, Zhenhai Zhu, Joel R. Phillips
2008High-performance timing simulation of embedded software.
Jürgen Schnerr, Oliver Bringmann, Alexander Viehl, Wolfgang Rosenstiel
2008Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration.
Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic
2008How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.
Min Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor
2008IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.
Sung-Boem Park, Subhasish Mitra
2008Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study.
Zhanpeng Jin, Allen C. Cheng
2008Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability.
Yousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak
2008IntellBatt: towards smarter battery design.
Suman Kalyan Mandal, Praveen Bhojwani, Saraju P. Mohanty, Rabi N. Mahapatra
2008Keeping hot chips cool: are IC thermal problems hot air?
Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky
2008Latency and bandwidth efficient communication through system customization for embedded multiprocessors.
Chenjie Yu, Peter Petrov
2008Leakage power reduction using stress-enhanced layouts.
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
2008Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.
Min Ni, Seda Ogrenci Memik
2008Leveraging sequential equivalence checking to enable system-level to RTL flows.
Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla
2008Low power passive equalizer optimization using tritonic step response.
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
2008MAPS: an integrated framework for MPSoC application parallelization.
Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda
2008Many-core design from a thermal perspective.
Wei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron
2008Merging nodes under sequential observability.
Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton
2008Miss reduction in embedded processors through dynamic, power-friendly cache design.
Garo Bournoutian, Alex Orailoglu
2008Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts.
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang
2008Modeling crosstalk in statistical static timing analysis.
Ravikishore Gandikota, David T. Blaauw, Dennis Sylvester
2008Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
2008Multicore design is the challenge! what is the solution?
Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller
2008Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.
Seungwhun Paik, Youngsoo Shin
2008Multiple defect diagnosis using no assumptions on failing pattern characteristics.
Xiaochun Yu, R. D. (Shawn) Blanton
2008Multiprocessor performance estimation using hybrid simulation.
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008Multithreaded simulation for synchronous dataflow graphs.
Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya
2008N-variant IC design: methodology and applications.
Yousra Alkabani, Farinaz Koushanfar
2008Next generation wireless-multimedia devices: who is up for the challenge?
Juan C. Rey, Andreas Kuehlmann, Jan M. Rabaey, Cormac Conroy, Ted Vucurevich, Ikuya Kawasaki, Tuna B. Tarim
2008Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
2008On reliable modular testing with vulnerable test access mechanisms.
Lin Huang, Feng Yuan, Qiang Xu
2008On tests to detect via opens in digital CMOS circuits.
Sudhakar M. Reddy, Irith Pomeranz, Chen Liu
2008On the role of timing masking in reliable logic circuit design.
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2008Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications.
Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar
2008Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation.
Yan Chen, Fei Xie, Jin Yang
2008Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform.
Yu Pang, Katarzyna Radecka
2008Parallel programming: can we PLEASE get it right this time?
Tim Mattson, Michael Wrinn
2008Parallelizing CAD: a timely research agenda for EDA.
Bryan Catanzaro, Kurt Keutzer, Bor-Yiing Su
2008Parameterized timing analysis with general delay models and arbitrary variation sources.
Khaled R. Heloue, Farid N. Najm
2008Partial order reduction for scalable testing of systemC TLM designs.
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
2008Path smoothing via discrete optimization.
Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert
2008Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2008PicoCube: a 1 cm
Yuen-Hui Chee, Mike Koplow, Michael Mark, Nathan Pletcher, Mike Seeman, Fred L. Burghardt, Dan Steingart, Jan M. Rabaey, Paul K. Wright, Seth Sanders
2008Power gating scheduling for power/ground noise reduction.
Hailin Jiang, Malgorzata Marek-Sadowska
2008Pre-RTL formal verification: an intel experience.
Robert Beers
2008Precise failure localization using automated layout analysis of diagnosis candidates.
Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
2008Predictive design space exploration using genetically programmed response surfaces.
Henry Cook, Kevin Skadron
2008Predictive dynamic thermal management for multicore systems.
Inchoon Yeo, Chih Chun Liu, Eun Jung Kim
2008Predictive formulae for OPC with applications to lithography-friendly routing.
Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
2008Predictive runtime verification of multi-processor SoCs in SystemC.
Alper Sen, Vinit Ogale, Magdy S. Abadir
2008Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems.
Shreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee
2008Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008
Limor Fix
2008Process variation tolerant SRAM array for ultra low voltage applications.
Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy
2008Programmable logic circuits based on ambipolar CNFET.
M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli
2008Protecting bus-based hardware IP by secret sharing.
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
2008Rapid application specific floating-point unit generation with bit-alignment.
Yee Jern Chong, Sri Parameswaran
2008Reconfigurable computing using content addressable memory for improved performance and resource usage.
Somnath Paul, Swarup Bhunia
2008Reinventing EDA with manycore processors.
Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou
2008Robust chip-level clock tree synthesis for SOC designs.
Anand Rajaram, David Z. Pan
2008Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.
Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang
2008Run-time instruction set selection in a transmutable embedded processor.
Lars Bauer, Muhammad Shafique, Jörg Henkel
2008SHIELD: a software hardware design methodology for security and reliability of MPSoCs.
Krutartha Patel, Sri Parameswaran
2008Scalable min-register retiming under timing and initializability constraints.
Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
2008Scan chain clustering for test power reduction.
Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding
2008Signature based Boolean matching in the presence of don't cares.
Afshin Abdollahi
2008Sparse matrix computations on manycore GPU's.
Michael Garland
2008Specify-explore-refine (SER): from specification to implementation.
Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara
2008Speedpath prediction based on learning from a small set of examples.
Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout
2008Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation.
Risto Savolainen, Tero Rissa
2008Statistical diagnosis of unmodeled systematic timing effects.
Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
2008Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.
Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao
2008Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations.
Xin Li, Hongzhou Liu
2008Statistical waveform and current source based standard cell models for accurate timing analysis.
Amit Goel, Sarma B. K. Vrudhula
2008Stochastic integral equation solver for efficient variation-aware interconnect extraction.
Tarek Moselhy, Luca Daniel
2008Stochastic modeling of a thermally-managed multi-core system.
Hwisung Jung, Peng Rong, Massoud Pedram
2008Strategies for mainstream usage of formal verification.
Raj S. Mitra
2008Study of the effects of MBUs on the reliability of a 150 nm SRAM device.
Juan Antonio Maestro, Pedro Reviriego
2008Symbolic noise analysis approach to computational hardware optimization.
Arash Ahmadi, Mark Zwolinski
2008SystemClick: a domain-specific framework for early exploration using functional performance models.
Christian Sauer, Matthias Gries, Hans-Peter Löb
2008SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models.
Christian Haubelt, Thomas Schlichter, Joachim Keinert, Michael Meredith
2008SystemVerilog implicit port enhancements accelerate system design & verification.
Clifford E. Cummings
2008Techniques for fully integrated intra-/inter-chip optical communication.
Claudio Favi, Edoardo Charbon
2008Technology exploration for graphene nanoribbon FETs.
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
2008Temperature management in multiprocessor SoCs using online learning.
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross
2008Tera-scale computing and interconnect challenges.
Jerry Bautista
2008The design of a low power carbon nanotube chemical sensor system.
Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan
2008The mixed signal optimum energy point: voltage and parallelism.
Brian P. Ginsburg, Anantha P. Chandrakasan
2008The synthesis of robust polynomial arithmetic with stochastic logic.
Weikang Qian, Marc D. Riedel
2008Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni
2008Topological routing to maximize routability for package substrate.
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
2008Topology synthesis of analog circuits based on adaptively generated building blocks.
Angan Das, Ranga Vemuri
2008Towards a more physical approach to gate modeling for timing, noise, and power.
Peter Feldmann, Soroush Abbaspour
2008Towards acceleration of fault simulation using graphics processing units.
Kanupriya Gulati, Sunil P. Khatri
2008Transistor level gate modeling for accurate and fast timing, noise, and power analysis.
Shiva Raja, F. Varadi, Murat R. Becer, Joao Geada
2008Translation of an existing VMM-based SystemVerilog testbench to OVM.
Kelly D. Larson
2008TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.
Stephen Bijansky, Adnan Aziz
2008Tunneling and slicing: towards scalable BMC.
Malay K. Ganai, Aarti Gupta
2008Type-matching clock tree for zero skew clock gating.
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu
2008Variation-adaptive feedback control for networks-on-chip with multiple clock domains.
Ümit Y. Ogras, Radu Marculescu, Diana Marculescu
2008Verifying really complex systems: on earth and beyond.
Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman
2008Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo
2008WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines.
Wei Dong, Peng Li, Xiaoji Ye
2008Why should we do 3D integration?
Wilfried Haensch
2008iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen