DAC A*

202 papers

YearTitle / Authors
2007"There Is More Than Moore In Automotive ...".
Hartmut Hiller
2007A DFT Method for Time Expansion Model at Register Transfer Level.
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
2007A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis.
Guo Yu, Wei Dong, Zhuo Feng, Peng Li
2007A Framework for the Validation of Processor Architecture Compliance.
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled
2007A Fully-Automated Desynchronization Flow for Synchronous Circuits.
Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou
2007A General Framework for Spatial Correlation Modeling in VLSI Design.
Frank Liu
2007A Memory-Conscious Code Parallelization Scheme.
Liping Xue, Ozcan Ozturk, Mahmut T. Kandemir
2007A New Twisted Differential Line Structure in Global Bus Design.
Zhanyuan Jiang, Shiyan Hu, Weiping Shi
2007A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
2007A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.
Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang
2007A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip.
Praveen Bhojwani, Rabi N. Mahapatra
2007A Self-Tuning Configurable Cache.
Ann Gordon-Ross, Frank Vahid
2007A System For Coarse Grained Memory Protection In Tiny Embedded Processors.
Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani B. Srivastava
2007A Unified Approach to Canonical Form-based Boolean Matching.
Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto
2007ASIP Instruction Encoding for Energy and Area Reduction.
Paul Morgan, Richard Taylor
2007Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning.
Wei Dong, Peng Li
2007Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
2007Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
2007Alembic: An Efficient Algorithm for CNF Preprocessing.
HyoJung Han, Fabio Somenzi
2007An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires.
Krishnan Sundaresan, Nihar R. Mahapatra
2007An Effective Guidance Strategy for Abstraction-Guided Simulation.
Flavio M. de Paula, Alan J. Hu
2007An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model.
Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo
2007An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.
Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin
2007An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
2007Analog Placement Based on Novel Symmetry-Island Formulation.
Mark Po-Hung Lin, Shyh-Chang Lin
2007Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.
Mingoo Seok, Scott Hanson, Dennis Sylvester, David T. Blaauw
2007Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures.
Christopher Ostler, Karam S. Chatha
2007Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra
2007Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling.
Peter Hallschmid, Resve A. Saleh
2007Automatic Verification of External Interrupt Behaviors for Microprocessor Design.
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
2007Automotive Software Integration.
Razvan Racu, Arne Hamann, Rolf Ernst, Kai Richter
2007Autonomous Automobiles: Developing Cars That Drive Themselves.
Dave Ferguson
2007Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.
Amith Singhee, Rob A. Rutenbar
2007CAD Implications of New Interconnect Technologies.
Louis Scheffer
2007CAD-based Security, Cryptography, and Digital Rights Management.
Farinaz Koushanfar, Miodrag Potkonjak
2007Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy
2007Characterizing Process Variation in Nanometer CMOS.
Kanak Agarwal, Sani R. Nassif
2007Chip Multi-Processor Generator.
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
2007Clock Period Minimization with Minimum Delay Insertion.
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
2007Compact State Machines for High Performance Pattern Matching.
Piti Piyachon, Yan Luo
2007Comparative Analysis of Conventional and Statistical Design Techniques.
Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
2007Computationally Efficient Power Integrity Simulation for System-on-Package Applications.
Krishna Bharath, Ege Engin, Madhavan Swaminathan, Kazuhide Uriu, Toru Yamada
2007Computer-aided Architecture Design & Optimized Implementation of Distributed Automotive EE Systems.
Antal Rajnak, Ajay Kumar
2007Concurrent Wire Spreading, Widening, and Filling.
Olivier Rizzo, Hanno Melzner
2007Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations.
Qunzeng Liu, Sachin S. Sapatnekar
2007Corezilla: Build and Tame the Multicore Beast?
Lauren Sarno, Wen-mei W. Hwu, Craig Lund, Markus Levy, James R. Larus, James Reinders, Gordon Cameron, Chris Lennard, Takashi Yoshimori
2007Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
2007DDBDD: Delay-Driven BDD Synthesis for FPGAs.
Lei Cheng, Deming Chen, Martin D. F. Wong
2007Design Methodology for Pipelined Heterogeneous Multiprocessor System.
Seng Lin Shee, Sri Parameswaran
2007Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.
Hamed F. Dadgour, Kaustav Banerjee
2007Design for Verification in System-level Models and RTL.
Anmol Mathur, Venkat Krishnaswamy
2007Design of Rotary Clock Based Circuits.
Zhengtao Yu, Xun Liu
2007Design without Borders - A Tribute to the Legacy of A. Richard Newton.
Jan M. Rabaey
2007Design-Silicon Timing Correlation A Data Mining Perspective.
Li-C. Wang, Pouria Bastani, Magdy S. Abadir
2007Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification.
Pramod Chandraiah, Rainer Dömer
2007Designing a New Automotive DNA.
Lawrence D. Burns
2007Dynamic Power Management with Hybrid Power Sources.
Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang
2007EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure.
Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao
2007Early Power-Aware Design & Validation: Myth or Reality?
Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis
2007Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.
Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
2007Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs.
Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit
2007Efficient Modeling Techniques for Dynamic Voltage Drop Analysis.
Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke
2007Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.
Xin Li, Lawrence T. Pileggi
2007Electronics: The New Differential in the Automotive Industry.
Nick Smith, Andrew Chien, Christopher Hegarty, Walden C. Rhines, Alberto L. Sangiovanni-Vincentelli, Frank Winters
2007Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design.
Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo
2007Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory.
Yongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck Chang
2007Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time.
Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li
2007Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands.
Lap-Fai Leung, Chi-Ying Tsui
2007Engineering synthetic killer circuits in bacteria.
Lingchong You
2007Enhancing FPGA Performance for Arithmetic Circuits.
Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar
2007Escape Routing For Dense Pin Clusters In Integrated Circuits.
Muhammet Mustafa Ozdal
2007Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks.
Brian Taylor, Larry T. Pileggi
2007Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application.
Juan R. Pimentel, Jason Paskvan
2007Extraction of Statistical Timing Profiles Using Test Data.
Ying-Yen Chen, Jing-Jia Liou
2007Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.
Nancy Ying Zhou, Zhuo Li, Weiping Shi
2007Fast Min-Cost Buffer Insertion under Process Variations.
Ruiming Chen, Hai Zhou
2007Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction.
Zhuo Feng, Peng Li, Yaping Zhan
2007Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch.
Jaeha Kim, Kevin D. Jones, Mark A. Horowitz
2007Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang
2007FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs.
Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst
2007Formal Techniques for SystemC Verification; Position Paper.
Moshe Y. Vardi
2007Functional Verification of SiCortex Multiprocessor System-on-a-Chip.
Oleg Petlin, Wilson Snyder
2007Gate Sizing For Cell Library-Based Designs.
Shiyan Hu, Mahesh Ketkar, Jiang Hu
2007GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.
Lei Cheng, Deming Chen, Martin D. F. Wong
2007Global Critical Path: A Tool for System-Level Timing Analysis.
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, Seth Copen Goldstein
2007Hardware Support for Secure Processing in Embedded Systems.
Shufu Mao, Tilman Wolf
2007High Performance and Low Power Electronics on Flexible Substrate.
Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
2007How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.
Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
2007IP Exchange: I'll Show You Mine if You Show Me Yours.
Lauren Sarno, Ron Wilson, Soo-Kwan Eo, Laurent Lestringand, John Goodenough, Guri Stark, Serge Leef, Dave Witt
2007IPR: An Integrated Placement and Routing Algorithm.
Min Pan, Chris C. N. Chu
2007Implicitly Parallel Programming Models for Thousand-Core Microprocessors.
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel
2007Improving Voltage Assignment by Outlier Detection and Incremental Placement.
Huaizhi Wu, Martin D. F. Wong
2007Instruction Splitting for Efficient Code Compression.
Talal Bonny, Jörg Henkel
2007Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.
Tao Xu, Krishnendu Chakrabarty
2007Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation.
Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
2007Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.
Kyoung-Hwan Lim, Yonghwan Kim, Taewhan Kim
2007Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Kerry Bernstein, Paul S. Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young
2007Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.
Shweta Srivastava, Jaijeet S. Roychowdhury
2007Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT.
Théodore Marescaux, Henk Corporaal
2007Language Extensions to SystemC: Process Control Constructs.
Bishnupriya Bhattacharya, John Rose, Stuart Swan
2007Layered Switching for Networks on Chip.
Zhonghai Lu, Ming Liu, Axel Jantsch
2007Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation.
Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange
2007Line-End Shortening is Not Always a Failure.
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
2007MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
2007Making Manufacturing Work For You.
Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
2007Megatrends and EDA 2017.
Francine Bacchini, Gregory S. Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada
2007Memory Modeling in ESL-RTL Equivalence Checking.
Alfred Kölbl, Jerry R. Burch, Carl Pixley
2007Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations.
Jaijeet S. Roychowdhury
2007Model-driven Validation of SystemC Designs.
Hiren D. Patel, Sandeep K. Shukla
2007Modeling Litho-Constrained Design Layout.
Min-Chun Tsai, Daniel Zhang, Zongwu Tang
2007Modeling Safe Operating Area in Hardware Description Languages.
Leonid B. Goldgeisser, Ernst Christen, Zhichao Deng
2007Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.
Henry H. Y. Chan, Zeljko Zilic
2007Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
2007Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.
Khaled R. Heloue, Navid Azizi, Farid N. Najm
2007Modeling the Function Cache for Worst-Case Execution Time Analysis.
Raimund Kirner, Martin Schoeberl
2007Multi-Core Design Automation Challenges.
John A. Darringer
2007Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs.
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal
2007NBTI-Aware Synthesis of Digital Circuits.
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2007NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
Wei Zhang, Li Shang, Niraj K. Jha
2007Nanometer Device Scaling in Subthreshold Circuits.
Scott Hanson, Mingoo Seok, Dennis Sylvester, David T. Blaauw
2007New Test Data Decompressor for Low Power Applications.
Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2007Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
Lerong Cheng, Jinjun Xiong, Lei He
2007Novel CNTFET-based Reconfigurable Logic Gate Design.
Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot
2007OPC-Free and Minimally Irregular IC Design Style.
Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
2007Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.
Hao Yu, Chunta Chu, Lei He
2007On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.
Ashesh Rastogi, Wei Chen, Sandip Kundu
2007On Resolution Proofs for Combinational Equivalence.
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
2007On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
2007On-Chip Measurements Complementary to Design Flow for Integrity in SoCs.
Makoto Nagata
2007On-The-Fly Resolve Trace Minimization.
Ohad Shacham, Karen Yorav
2007Optimal Selection of Voltage Regulator Modules in a Power Delivery Network.
Behnam Amelifard, Massoud Pedram
2007Optimization of Area in Digital FIR Filters using Gate-Level Metrics.
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2007Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking.
Zonghua Gu, Xiuqiang He, Mingxuan Yuan
2007PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels.
Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury
2007Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.
Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
2007Parameterized Macromodeling for Analog System-Level Design Exploration.
Jian Wang, Xin Li, Lawrence T. Pileggi
2007Performance Analysis of FlexRay-based ECU Networks.
Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh
2007Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.
Azad Naeemi, Reza Sarvari, James D. Meindl
2007Period Optimization for Hard Real-time Distributed Automotive Systems.
Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto L. Sangiovanni-Vincentelli
2007Perspective of the Future Semiconductor Industry: Challenges and Solutions.
Oh-Hyun Kwon
2007Physical Unclonable Functions for Device Authentication and Secret Key Generation.
G. Edward Suh, Srinivas Devadas
2007Placement of 3D ICs with Thermal and Interlayer Via Considerations.
Brent Goplen, Sachin S. Sapatnekar
2007Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007
2007Program Mapping onto Network Processors by Recursive Bipartitioning and Refining.
Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang
2007Programming Living Cells to Function as Massively Parallel Computers.
Jeffrey J. Tabor
2007Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical Experiment.
Dmitri Maslov, Sean M. Falconer, Michele Mosca
2007Quantum-Like Effects in Network-on-Chip Buffers Behavior.
Paul Bogdan, Radu Marculescu
2007RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks.
Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2007RISPP: Rotating Instruction Set Processing Platform.
Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel
2007RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
2007Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution.
Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi, Santanu Dutta
2007Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.
Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk
2007Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver.
Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng
2007SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.
Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy
2007SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
2007SODA: Sensitivity Based Optimization of Disk Architecture.
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan
2007Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.
Kiran Puttaswamy, Gabriel H. Loh
2007Scan Test Planning for Power Reduction.
Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
2007Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera
2007Self-Resetting Latches for Asynchronous Micro-Pipelines.
Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein
2007Shared Resource Access Attributes for High-Level Contention Models.
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
2007Side-Channel Attack Pitfalls.
Kris Tiri
2007Silicon Speedpath Measurement and Feedback into EDA flows.
Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout
2007Simulating Improbable Events.
Suwen Yang, Mark R. Greenstreet
2007Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.
Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya
2007Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.
Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert
2007Single-Event-Upset (SEU) Awareness in FPGA Routing.
Shahin Golshan, Elaheh Bozorgzadeh
2007Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.
Jun Seomun, Jaehyun Kim, Youngsoo Shin
2007Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage.
Tao Li, Zhiping Yu
2007Statistical Framework for Technology-Model-Product Co-Design and Convergence.
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski
2007Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.
Xiaoji Ye, Yaping Zhan, Peng Li
2007Synchronous Elastic Circuits with Early Evaluation and Token Counterflow.
Jordi Cortadella, Michael Kishinevsky
2007Synthesizing SVA Local Variables for Formal Verification.
Jiang Long, Andrew Seawright
2007Synthesizing Stochasticity in Biochemical Systems.
Brian Fett, Jehoshua Bruck, Marc D. Riedel
2007Synthetic biology: from bacteria to stem cells.
Ron Weiss
2007System-Level Design Flow Based on a Functional Reference for HW and SW.
Walter H. Tibboel, Víctor Reyes, Martin Klompstra, Dennis Alders
2007System-on-Chip Power Management Considering Leakage Power Variations.
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2007TLM: Crossing Over From Buzz To Adoption.
Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil
2007TROY: Track Router with Yield-driven Wire Planning.
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
2007Techniques for Effective Distributed Physical Synthesis.
Freddy Y. C. Mang, Wenting Hou, Pei-Hsin Ho
2007Test Generation in the Presence of Timing Exceptions and Constraints.
Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
2007The Case for Low-Power Photonic Networks on Chip.
Assaf Shacham, Keren Bergman, Luca P. Carloni
2007The Case for the Precision Timed (PRET) Machine.
Stephen A. Edwards, Edward A. Lee
2007The Impact of NBTI on the Performance of Combinational and Sequential Circuits.
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2007The KILL Rule for Multicore.
Anant Agarwal, Markus Levy
2007Thousand Core ChipsA Technology Perspective.
Shekhar Borkar
2007Top-k Aggressors Sets in Delay Noise Analysis.
Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer
2007Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System.
Rebecca L. Collins, Luca P. Carloni
2007Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors.
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Robert G. Knobel
2007Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2007Trusted Design in FPGAs.
Steven Trimberger
2007Trusted Hardware: Can It Be Trustworthy?
Cynthia E. Irvine, Karl N. Levitt
2007Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.
Tomasz S. Czajkowski, Stephen Dean Brown
2007Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.
Kunhyuk Kang, Keejong Kim, Kaushik Roy
2007Verification Coverage: When is Enough, Enough?
Francine Bacchini, Alan J. Hu, Tom Fitzpatrick, Rajeev Ranjan, David Lacey, Mercedes Tan, Andrew Piziali, Avi Ziv
2007Verification Methodologies in a TLM-to-RTL Design Flow.
Atsushi Kasuya, Tesh Tesfaye
2007Virtual Platforms and Timing Analysis: Status, Challenges and Future Directions.
Marco Di Natale
2007Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip.
Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu
2007Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
2007You Can Get There From Here: Connectivity of Random Graphs on Grids.
Steven P. Levitan