DAC A*

220 papers

YearTitle / Authors
2006"The IC nanometer race -- what will it take to win?".
Gadi Singer, Philippe Magarshack, Dennis Buss, Fu-Chieh Hsu, Ho-Kyu Kang
20064.25 Gb/s laser driver: design challenges and EDA tool limitations.
Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann
2006A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW.
Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni
2006A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications.
Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho
2006A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2006A PLA based asynchronous micropipelining approach for subthreshold circuit design.
Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
2006A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss
2006A design approach for radiation-hard digital electronics.
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
2006A family of cells to reduce the soft-error-rate in ternary-CAM.
Navid Azizi, Farid N. Najm
2006A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.
David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias
2006A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
2006A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils.
Ngai Wong, C. K. Chu
2006A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
2006A flexible and scalable methodology for GHz-speed structural test.
Vikram Iyengar, Gary Grise, Mark Taylor
2006A framework for embedded system specification under different models of computation in SystemC.
Fernando Herrera, Eugenio Villar
2006A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.
Hari Ananthan, Kaushik Roy
2006A high density, carbon nanotube capacitor for decoupling applications.
Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
2006A model-driven design environment for embedded systems.
Elvinia Riccobene, Patrizia Scandurra, Alberto Rosti, Sara Bocchio
2006A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.
Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
2006A multi-port current source model for multiple-input switching effects in CMOS library cells.
Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
2006A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators.
Xiaolue Lai, Jaijeet S. Roychowdhury
2006A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
2006A network security processor design based on an integrated SOC design and test platform.
Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006A new LP based incremental timing driven placement for high performance designs.
Tao Luo, David Newmark, David Z. Pan
2006A new hybrid FPGA with nanoscale clusters and CMOS routing.
Reza M. Rad, Mohammad Tehranipoor
2006A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates.
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
2006A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures.
Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala
2006A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
2006A real time budgeting method for module-level-pipelined bus based system using bus scenarios.
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino
2006A reconfigurable design-for-debug infrastructure for SoCs.
Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
2006A robust envelope following method applicable to both non-autonomous and oscillatory circuits.
Ting Mei, Jaijeet S. Roychowdhury
2006A systematic method for functional unit power estimation in microprocessors.
Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
2006A test pattern ordering algorithm for diagnosis with truncated fail data.
Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
2006An IC manufacturing yield model considering intra-die variations.
Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang
2006An adaptive FPGA architecture with process variation compensation and reduced leakage.
Georges Nabaa, Navid Azizi, Farid N. Najm
2006An automated, reconfigurable, low-power RFID tag.
Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
2006An efficient and versatile scheduling algorithm based on SDC formulation.
Jason Cong, Zhiru Zhang
2006An efficient retiming algorithm under setup and hold constraints.
Chuan Lin, Hai Zhou
2006An up-stream design auto-fix flow for manufacturability enhancement.
Jie Yang, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig
2006Architecture-aware FPGA placement using metric embedding.
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
2006Are carbon nanotubes the future of VLSI interconnections?
Kaustav Banerjee, Navin Srivastava
2006Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*.
William L. Hwang, Fei Su, Krishnendu Chakrabarty
2006Automatic invariant strengthening to prove properties in bounded model checking.
Mohammad Awedh, Fabio Somenzi
2006Backlight dimming in power-aware mobile displays.
Ali Iranli, Wonbok Lee, Massoud Pedram
2006Behavior and communication co-optimization for systems with sequential communication media.
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006BoxRouter: a new global router based on box expansion and progressive ILP.
Minsik Cho, David Z. Pan
2006Budgeting-free hierarchical design method for large scale and high-performance LSIs.
Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa
2006Buffer insertion in large circuits with constructive solution search techniques.
Mandar Waghmode, Zhuo Li, Weiping Shi
2006Buffer memory optimization for video codec application modeled in Simulink.
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya
2006Building a standard ESL design and verification methodology: is it just a dream?
Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch
2006Building a verification test plan: trading brute force for finesse.
Janick Bergeron, Harry Foster, Andrew Piziali, Raj Shekher Mitra, Catherine Ahlschlager, Doron Stein
2006CAD challenges for leading-edge multimedia designs.
Andrew B. Kahng
2006Challenges in sleep transistor design and implementation in low-power designs.
Kaijian Shi, David Howard
2006Chameleon ART: a non-optimization based analog design migration framework.
Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein
2006Charge recycling in MTCMOS circuits: concept and analysis.
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
2006Circuit simulation based obstacle-aware Steiner routing.
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
2006Circuits for energy harvesting sensor signal processing.
Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou
2006Clock buffer and wire sizing using sequential programming.
Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
2006Communication latency aware low power NoC synthesis.
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
2006Computation of accurate interconnect process parameter values for performance corners under process variations.
Frank Huebbers, Ali Dasdan, Yehea I. Ismail
2006Configurable cache subsetting for fast cache tuning.
Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid
2006Constraint-driven floorplan repair.
Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack
2006Criticality computation in parameterized statistical timing.
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
2006DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006DFM: where's the proof of value?
Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan
2006DFT for controlled-impedance I/O buffers.
Ahmad A. Al-Yamani
2006Decision-making for complex SoCs in consumer electronic products.
Ron Wilson, Yervant Zorian
2006Design automation for DNA self-assembled nanostructures.
Constantin Pistol, Alvin R. Lebeck, Chris Dwyer
2006Design challenges for next-generation multimedia, game and entertainment platforms.
John M. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, Brendan Traw
2006Design in reliability for communication designs.
Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar
2006Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
2006Design space exploration and prototyping for on-chip multimedia applications.
Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang
2006Design space exploration using time and resource duality with the ant colony optimization.
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner
2006Design tools for reliability analysis.
Zhihong Liu, Bruce McGaughy, James Z. Ma
2006Directed-simulation assisted formal verification of serial protocol and bridge.
Saurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra
2006Distributed dynamic BDD reordering.
Ziv Nevo, Monica Farkash
2006DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip.
Ming Li, Qing-An Zeng, Wen-Ben Jone
2006Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.
Xiushan Feng, Alan J. Hu
2006Efficient SAT-based Boolean matching for FPGA technology mapping.
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
2006Efficient detection and exploitation of infeasible paths for software timing analysis.
Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
2006Efficient escape routing for hexagonal array of high density I/Os.
Rui Shi, Chung-Kuan Cheng
2006Efficient simulation of critical synchronous dataflow graphs.
Chia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya
2006Electronics beyond nano-scale CMOS.
Shekhar Borkar
2006Elmore model for energy estimation in RC trees.
Quming Zhou, Kartik Mohanram
2006Energy-scalable OFDM transmitter design and control.
Björn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd Vandersteen, Francky Catthoor
2006Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP.
Michaël Goffioul, Gerd Vandersteen, Joris Van Driessche, Björn Debaillie, Boris Come
2006Entering the hot zone - can you handle the heat and be cool?
Andrew Yang, Rajit Chandra, Simon Burke, Javier A. DeLaCruz, Sribalan Santhanam, Uming Ko
2006Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs.
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
2006Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection.
Kuo-Hua Wang
2006Exploiting forwarding to improve data bandwidth of instruction-set extensions.
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
2006Exploring compromises among timing, power and temperature in three-dimensional integrated circuits.
Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis
2006Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs.
Sander Stuijk, Marc Geilen, Twan Basten
2006Extending the lifetime of fuel cell based hybrid systems.
Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
2006ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling.
Kui Wang, Lian Duan, Xu Cheng
2006FLAW: FPGA lifetime awareness.
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
2006Fast algorithms for slew constrained minimum cost buffering.
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2006Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
Hao Yu, Yiyu Shi, Lei He
2006Fast falsification based on symbolic bounded property checking.
Prakash Mohan Peranandam, Pradeep Kumar Nalla, Jürgen Ruf, Roland Weiss, Thomas Kropf, Wolfgang Rosenstiel
2006Fast illegal state identification for improving SAT-based induction.
Vishnu C. Vimjam, Michael S. Hsiao
2006Fault detection and diagnosis with parity trees for space compaction of test responses.
Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
2006Formal analysis of hardware requirements.
Ingo Pill, Simone Semprini, Roberto Cavada, Marco Roveri, Roderick Bloem, Alessandro Cimatti
2006Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
2006Games are up for DVFS.
Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
2006Gate sizing: finFETs vs 32nm bulk MOSFETs.
Brian Swahn, Soha Hassoun
2006Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
2006GreenBus: a generic interconnect fabric for transaction level modelling.
Wolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton
2006Guiding simulation with increasingly refined abstract traces.
Kuntal Nanshi, Fabio Somenzi
2006Harvesting aware power management for sensor networks.
Aman Kansal, Jason Hsu, Mani B. Srivastava, Vijay Raghunathan
2006Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2006Hierarchical power distribution and power management scheme for a single chip mobile processor.
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
2006High-level power management of embedded systems with application-specific energy cost functions.
Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula
2006High-performance operating system controlled memory compression.
Lei Yang, Haris Lekatsas, Robert P. Dick
2006Hold time validation on silicon and the relevance of hazards in timing analysis.
Amitava Majumdar, Wei-Yu Chen, Jun Guo
2006How will the fabless model survive?
Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu
2006HybDTM: a coordinated hardware-software approach for dynamic thermal management.
Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha
2006IMPRES: integrated monitoring for processor reliability and security.
Roshan G. Ragel, Sri Parameswaran
2006Leakage power reduction of embedded memories on FPGAs through location assignment.
Yan Meng, Timothy Sherwood, Ryan Kastner
2006Leakage-aware intraprogram voltage scaling for embedded processors.
Po-Kuan Huang, Soheil Ghiasi
2006Lookup table based simulation and statistical modeling of Sigma-Delta ADCs.
Guo Yu, Peng Li
2006Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.
Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2006Low-power bus encoding using an adaptive hybrid algorithm.
Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu
2006Low-power repeater insertion with both delay and slew rate constraints.
Yuantao Peng, Xun Liu
2006MARS-C: modeling and reduction of soft errors in combinational circuits.
Natasa Miskov-Zivanov, Diana Marculescu
2006Maintaining consistency between systemC and RTL system designs.
Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard
2006Minimization for LED-backlit TFT-LCDs.
Wei-Chung Cheng, Chain-Fu Chao
2006Mining global constraints for improving bounded sequential equivalence checking.
Weixin Wu, Michael S. Hsiao
2006Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2006Model order reduction of linear networks with massive ports via frequency-dependent port packing.
Peng Li, Weiping Shi
2006Modeling and analysis of circuit performance of ballistic CNFET.
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
2006Modeling and minimization of PMOS NBTI effect for robust nanometer design.
Rakesh Vattikonda, Wenping Wang, Yu Cao
2006Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
2006Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation.
Ngai Wong, Venkataramanan Balakrishnan
2006Multiple-detect ATPG based on physical neighborhoods.
Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
2006Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt
2006NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
Wei Zhang, Niraj K. Jha, Li Shang
2006Novel full-chip gridless routing considering double-via insertion.
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
2006Optimal cell flipping in placement and floorplanning.
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
2006Optimal jumper insertion for antenna avoidance under ratio upper-bound.
Jia Wang, Hai Zhou
2006Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems.
Lap-Fai Leung, Chi-Ying Tsui
2006Optimal simultaneous mapping and clustering for FPGA delay optimization.
Joey Y. Lin, Deming Chen, Jason Cong
2006Optimality study of resource binding with multi-Vdds.
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
2006Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2006Optimizing code parallelization through a constraint network based approach.
Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir
2006Overview of the MPSoC design challenge.
Grant Martin
2006PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.
William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
2006Physical design methodology of power gating circuits for standard-cell-based design.
Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo
2006Placement of digital microfluidic biochips using the t-tree formulation.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2006Power grid physics and implications for CAD.
Sanjay Pant, Eli Chiprout
2006Power-centric design of high-speed I/Os.
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang
2006Practical aspects of reliability analysis for IC designs.
Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider
2006Practical methods in coverage-oriented verification of the merom microprocessor.
Alon Gluska
2006Predicate learning and selective theory deduction for a difference logic solver.
Chao Wang, Aarti Gupta, Malay K. Ganai
2006Prediction-based flow control for network-on-chip traffic.
Ümit Y. Ogras, Radu Marculescu
2006Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools.
Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
2006Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006
Ellen Sentovich
2006Process variation aware OPC with variational lithography modeling.
Peng Yu, Sean X. Shi, David Z. Pan
2006Programming models and HW-SW interfaces abstraction for multi-processor SoC.
Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot
2006Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.
Xin Li, Jiayong Le, Lawrence T. Pileggi
2006Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery.
Xinping Zhu, Wei Qin
2006Rapid and low-cost context-switch through embedded processor customization for real-time and control applications.
Xiangrong Zhou, Peter Petrov
2006Rapid estimation of control delay from high-level specifications.
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
2006Refined statistical static timing analysis through.
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2006Register binding for clock period minimization.
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
2006Reliability challenges for 45nm and beyond.
J. W. McPherson
2006Reliability modeling and management in dynamic microprocessor-based systems.
Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2006SAT sweeping with local observability don't-cares.
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli
2006SMERT: energy-efficient design of a multimedia messaging system for mobile devices.
Lin Zhong, Bin Wei, Michael J. Sinclair
2006SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers.
Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
2006Scheduling-based test-case generation for verification of multimedia SoCs.
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen
2006Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy
2006Shielding against design flaws with field repairable control logic.
Ilya Wagner, Valeria Bertacco, Todd M. Austin
2006Signature-based workload estimation for mobile 3D graphics.
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
2006Silicon carrier for computer systems.
Chirag S. Patel
2006Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.
Yu Hu, Yan Lin, Lei He, Tim Tuan
2006Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2006Solution-processed infrared photovoltaic devices.
Dean D. MacNeil, Edward H. Sargent
2006Standard cell characterization considering lithography induced variations.
Ke Cao, Sorin Dobre, Jiang Hu
2006Standard cell library optimization for leakage reduction.
Saumil Shah, Puneet Gupta, Andrew B. Kahng
2006State encoding of large asynchronous controllers.
Josep Carmona, Jordi Cortadella
2006Statistical analysis of SRAM cell stability.
Kanak Agarwal, Sani R. Nassif
2006Statistical logic cell delay analysis using a current-based model.
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
2006Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.
Sujan Pandey, Manfred Glesner
2006Statistical timing analysis with correlated non-gaussian parameters using independent component analysis.
Jaskirat Singh, Sachin S. Sapatnekar
2006Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
2006Steiner network construction for timing critical nets.
Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
2006Stochastic variational analysis of large power grids considering intra-die correlations.
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
2006Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2006Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2006Synthesis of high-performance packet processing pipelines.
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
2006Synthesis of synchronous elastic architectures.
Jordi Cortadella, Michael Kishinevsky, Bill Grundmann
2006System level signal and power integrity analysis methodology for system-in-package applications.
Rohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, Madhavan Swaminathan
2006System-level exploration tools for MPSoC designs.
Peter Flake, Simon J. Davidmann, Frank Schirrmeister
2006SystemC transaction level models and RTL verification.
Stuart Swan
2006Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.
Ying Wei, Alex Doboli
2006Systematic software-based self-test for pipelined processors.
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2006Systematic temperature sensor allocation and placement for microprocessors.
Rajarshi Mukherjee, Seda Ogrenci Memik
2006Systems for human-powered mobile computing.
Joseph A. Paradiso
2006Test generation games from formal specifications.
Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta
2006Test response compactor with programmable selector.
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2006The good, the bad, and the ugly of silicon debug.
Doug Josephson
2006The importance of adopting a package-aware chip design flow.
Kaushik Sheth, Egino Sarto, Joel McGrath
2006The zen of nonvolatile memories.
Erwin J. Prinz
2006Timing driven power gating.
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
2006Timing-based delay test for screening small delay defects.
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2006Timing-constrained and voltage-island-aware voltage assignment.
Huaizhi Wu, Martin D. F. Wong, I-Min Liu
2006Timing-driven Steiner trees are (practically) free.
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
2006Tomorrow's analog: just dead or just different?
Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini
2006Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2006Towards a C++-based design methodology facilitating sequential equivalence checking.
Philippe Georgelin, Venkat Krishnaswamy
2006Towards the automatic exploration of arithmetic-circuit architectures.
Ajay Kumar Verma, Paolo Ienne
2006Tradeoffs and choices for emerging SoCs in high-end applications.
Nic Mokhoff, Yervant Zorian
2006Transistor abstraction for the functional verification of FPGAs.
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
2006Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei
2006Use of C/C++ models for architecture exploration and verification of DSPs.
David Brier, Raj S. Mitra
2006VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals.
Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro
2006Variability driven gate sizing for binning yield optimization.
Azadeh Davoodi, Ankur Srivastava
2006Variation-aware analysis: savior of the nanometer era?
Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
2006Verification of the cell broadband engine
Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson
2006Visibility enhancement for silicon debug.
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang