| 2005 | A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta |
| 2005 | A 24 GHz phased-array transmitter in 0.18µm CMOS. Arun Natarajan, Abbas Komijani, Ali Hajimiri |
| 2005 | A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. Rasit Onur Topaloglu, Alex Orailoglu |
| 2005 | A combined feasibility and performance macromodel for analog circuits. Mengmeng Ding, Ranga Vemuri |
| 2005 | A design platform for 90-nm leakage reduction techniques. Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko |
| 2005 | A general framework for accurate statistical timing analysis considering correlations. Vishal Khandelwal, Ankur Srivastava |
| 2005 | A generic micro-architectural test plan approach for microprocessor verification. Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet |
| 2005 | A green function-based parasitic extraction method for inhomogeneous substrate layers. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram |
| 2005 | A lattice-based framework for the classification and design of asynchronous pipelines. Peggy B. McGee, Steven M. Nowick |
| 2005 | A low latency router supporting adaptivity for on-chip interconnects. Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das |
| 2005 | A new canonical form for fast boolean matching in logic synthesis and verification. Afshin Abdollahi, Massoud Pedram |
| 2005 | A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter |
| 2005 | A non-parametric approach for dynamic range estimation of nonlinear systems. Bin Wu, Jianwen Zhu, Farid N. Najm |
| 2005 | A novel synthesis approach for active leakage power reduction using dynamic supply gating. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2005 | A pattern matching coprocessor for network security. Young H. Cho, William H. Mangione-Smith |
| 2005 | A quasi-convex optimization approach to parameterized model order reduction. Kin Cheong Sou, Alexandre Megretski, Luca Daniel |
| 2005 | A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
| 2005 | A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede |
| 2005 | A unified optimization framework for equalization filter synthesis. Jihong Ren, Mark R. Greenstreet |
| 2005 | A variation tolerant subthreshold design approach. Nikhil Jayakumar, Sunil P. Khatri |
| 2005 | A watermarking system for IP protection by a post layout incremental router. Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga |
| 2005 | Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director |
| 2005 | Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
| 2005 | Advanced timing analysis based on post-OPC extraction of critical dimensions. Jie Yang, Luigi Capodieci, Dennis Sylvester |
| 2005 | An effective DFM strategy requires accurate process and IP pre-characterization. Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara |
| 2005 | An effective power mode transition technique in MTCMOS circuits. Afshin Abdollahi, Farzan Fallah, Massoud Pedram |
| 2005 | An efficient algorithm for statistical minimization of total power under timing yield constraints. Murari Mani, Anirudh Devgan, Michael Orshansky |
| 2005 | An exact jumper insertion algorithm for antenna effect avoidance/fixing. Bor-Yiing Su, Yao-Wen Chang |
| 2005 | Analysis of full-wave conductor system impedance over substrate using novel integration techniques. Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel |
| 2005 | Application/architecture power co-optimization for embedded systems powered by renewable sources. Dexin Li, Pai H. Chou |
| 2005 | Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi |
| 2005 | Architecture-adaptive range limit windowing for simulated annealing FPGA placement. Kenneth Eguro, Scott Hauck, Akshay Sharma |
| 2005 | Are there economic benefits in DFM? Matt Nowak, Riko Radojcic |
| 2005 | Asynchronous circuits transient faults sensitivity evaluation. Yannick Monnet, Marc Renaudin, Régis Leveugle |
| 2005 | Automated nonlinear Macromodelling of output buffers for high-speed digital applications. Ning Dong, Jaijeet S. Roychowdhury |
| 2005 | Automatic generation of customized discrete fourier transform IPs. Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel |
| 2005 | Automatic scenario detection for improved WCET estimation. Stefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal |
| 2005 | BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. Tsutomu Sasao, Munehiro Matsuura |
| 2005 | BEOL variability and impact on RC extraction. N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill |
| 2005 | Beyond safety: customized SAT-based model checking. Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2005 | CAD tools for variation tolerance. David T. Blaauw, Kaviraj Chopra |
| 2005 | Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee |
| 2005 | Can we really do without the support of formal methods in the verification of large designs? Umberto Rossi |
| 2005 | Choosing flows and methodologies for SoC design. Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris |
| 2005 | Circuit optimization using statistical static timing analysis. Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov |
| 2005 | Closing the power gap between ASIC and custom: an ASIC perspective. David G. Chinnery, Kurt Keutzer |
| 2005 | Cognitive radio techniques for wide area networks. William Krenik, Anuj Batra |
| 2005 | Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. Chong Zhao, Yi Zhao, Sujit Dey |
| 2005 | Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede |
| 2005 | Correlation-aware statistical timing analysis with non-gaussian delay distributions. Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma |
| 2005 | Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen |
| 2005 | DC-DC converter-aware power management for battery-operated embedded systems. Yongseok Choi, Naehyuck Chang, Taewhan Kim |
| 2005 | DFM rules! Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan |
| 2005 | DTM: dynamic tone mapping for backlight scaling. Ali Iranli, Massoud Pedram |
| 2005 | Design methodology for IC manufacturability based on regular logic-bricks. V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi |
| 2005 | Design methodology for wireless nodes with printed antennas. Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic |
| 2005 | Designing logic circuits for probabilistic computation in the presence of noise. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
| 2005 | Deterministic approaches to analog performance space exploration (PSE). Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann |
| 2005 | Device and architecture co-optimization for FPGA power reduction. Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He |
| 2005 | DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala |
| 2005 | Differentiate and deliver: leveraging your partners. Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy |
| 2005 | Diffusion-based placement migration. Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia |
| 2005 | Dynamic abstraction using SAT-based BMC. Liang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle |
| 2005 | Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. Antonio Carlos Schneider Beck, Luigi Carro |
| 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. Ravindra Jejurikar, Rajesh K. Gupta |
| 2005 | ESL: building the bridge between systems to silicon. Francine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard |
| 2005 | Effective bounding techniques for solving unate and binate covering problems. Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez |
| 2005 | Efficient SAT solving: beyond supercubes. Domagoj Babic, Jesse D. Bingham, Alan J. Hu |
| 2005 | Efficient and accurate gate sizing with piecewise convex delay models. Hiran Tennakoon, Carl Sechen |
| 2005 | Efficient fingerprint-based user authentication for embedded systems. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | Energy optimal speed control of devices with discrete speed sets. Ravishankar Rao, Sarma B. K. Vrudhula |
| 2005 | Energy-effcient physically tagged caches for embedded processors with virtual memory. Peter Petrov, Daniel Tracy, Alex Orailoglu |
| 2005 | Enhanced leakage reduction Technique by gate replacement. Lin Yuan, Gang Qu |
| 2005 | Explaining the gap between ASIC and custom power: a custom perspective. Andrew Chang, William J. Dally |
| 2005 | Exploiting suspected redundancy without proving it. Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman |
| 2005 | Exploring technology alternatives for nano-scale FPGA interconnects. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin |
| 2005 | FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2005 | FPGA technology mapping: a study of optimality. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | Faster and better global placement by a new transportation algorithm. Ulrich Brenner, Markus Struzyna |
| 2005 | Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. Sorin Manolache, Petru Eles, Zebo Peng |
| 2005 | Fine-grained application source code profiling for ASIP design. Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2005 | Flexible ASIC: shared masking for multiple media processors. Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak |
| 2005 | Floorplan-aware automated synthesis of bus-based communication architectures. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane |
| 2005 | Formal verification: is it real enough? Yaron Wolfsthal, Rebecca M. Gott |
| 2005 | Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. Yuantao Peng, Xun Liu |
| 2005 | Frequency-based code placement for embedded multiprocessors. Corey Goldfeder |
| 2005 | From myth to methodology: cross-layer design for energy-efficient wireless communication. Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor |
| 2005 | Full-chip analysis of leakage power under process variations, including spatial correlations. Hongliang Chang, Sachin S. Sapatnekar |
| 2005 | Hardware speech recognition for user interfaces in low cost, low power devices. Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer |
| 2005 | High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian |
| 2005 | High performance encryption cores for 3G networks. Tomás Balderas-Contreras, René Cumplido |
| 2005 | How accurately can we model timing in a placement engine? Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin |
| 2005 | How to determine the necessity for emerging solutions. Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim |
| 2005 | Hybrid simulation for embedded software energy estimation. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2005 | ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen |
| 2005 | IODINE: a tool to automatically infer dynamic invariants for hardware designs. Sudheendra Hangal, Naveen Chandra, Sridhar Narayanan, Sandeep Chakravorty |
| 2005 | Implementing low-power configurable processors: practical options and tradeoffs. John Wei, Chris Rowen |
| 2005 | Improving java virtual machine reliability for memory-constrained embedded systems. Guangyu Chen, Mahmut T. Kandemir |
| 2005 | Incremental exploration of the combined physical and behavioral design space. Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou |
| 2005 | Incremental retiming for FPGA physical synthesis. Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown |
| 2005 | Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?". Navraj Nandra, Phil Dworsky, Rick Merritt, John F. D'Ambrosia, Adam Healey, Boris Litinsky, John T. Stonick, Joe Abler |
| 2005 | Is methodology the highway out of verification hell? Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso |
| 2005 | Keeping hot chips cool. Ruchir Puri, Leon Stok, Subhrajit Bhattacharya |
| 2005 | Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. Yan Lin, Lei He |
| 2005 | Leakage minimization of nano-scale circuits in the presence of systematic and random variations. Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2005 | Leakage power optimization with dual-V Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee |
| 2005 | Locality-conscious workload assignment for array-based computations in MPSOC architectures. Feihui Li, Mahmut T. Kandemir |
| 2005 | Logic block clustering of large designs for channel-width constrained FPGAs. Marvin Tom, Guy G. Lemieux |
| 2005 | Logic soft errors in sub-65nm technologies design and CAD challenges. Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang |
| 2005 | Low power network processor design using clock gating. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan |
| 2005 | MIMO technology for advanced wireless local area networks. Jeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun |
| 2005 | MP core: algorithm and design techniques for efficient channel estimation in wireless applications. Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner |
| 2005 | Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. Yu Cao, Lawrence T. Clark |
| 2005 | Matlab as a development environment for FPGA design. Tejas M. Bhatt, Dennis McCain |
| 2005 | Matlab extensions for the development, testing and verification of real-time DSP software. David P. Magee |
| 2005 | Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. Jungeun Kim, Taewhan Kim |
| 2005 | Microarchitecture-aware floorplanning using a statistical design of experiments approach. Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
| 2005 | MiniBit: bit-width optimization via affine arithmetic. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk |
| 2005 | Minimising buffer requirements of synchronous dataflow graphs with model checking. Marc Geilen, Twan Basten, Sander Stuijk |
| 2005 | Minimizing peak current via opposite-phase clock tree. Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
| 2005 | Mixed signal design space exploration through analog platforms. Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli |
| 2005 | Modular domain-specific implementation and exploration framework for embedded software platforms. Christian Sauer, Matthias Gries, Sören Sonntag |
| 2005 | Multi-frequency wrapper design and optimization for embedded cores under average power constraints. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty |
| 2005 | Multi-level approach for integrated spiral inductor optimization. Arthur Nieuwoudt, Yehia Massoud |
| 2005 | Multi-threaded reachability. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson |
| 2005 | Multilevel full-chip routing for the X-based architecture. Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen |
| 2005 | Multiplexer restructuring for FPGA implementation cost reduction. Paul Metzgen, Dominic Nancekievill |
| 2005 | N-detection under transparent-scan. Irith Pomeranz |
| 2005 | Navigating registers in placement for clock network minimization. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | Net weighting to reduce repeater counts during placement. Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
| 2005 | Normalization at the arithmetic bit level. Markus Wedler, Dominik Stoffel, Wolfgang Kunz |
| 2005 | OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi |
| 2005 | On the need for statistical timing analysis. Farid N. Najm |
| 2005 | Operator-based model-order reduction of linear periodically time-varying systems. Yayun Wan, Jaijeet S. Roychowdhury |
| 2005 | Optimal procrastinating voltage scheduling for hard real-time systems. Yan Zhang, Zhijian Lu, John C. Lach, Kevin Skadron, Mircea R. Stan |
| 2005 | Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah |
| 2005 | Partitioning-based approach to fast on-chip decap budgeting and minimization. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong |
| 2005 | Path based buffer insertion. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
| 2005 | Path delay test compaction with process variation tolerance. Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
| 2005 | Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. Ho Young Kim, Tag Gon Kim |
| 2005 | Performance space modeling for hierarchical synthesis of analog integrated circuits. Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert |
| 2005 | Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt |
| 2005 | Piece-wise approximations of RLCK circuit responses using moment matching. Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu |
| 2005 | Power emulation: a new paradigm for power estimation. Joel Coburn, Srivaths Ravi, Anand Raghunathan |
| 2005 | Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation. Peng Li |
| 2005 | Power optimal dual-Vdd buffered tree considering buffer stations and blockages. King Ho Tam, Lei He |
| 2005 | Power-aware placement. Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang |
| 2005 | Prime clauses for fast enumeration of satisfying assignments to boolean circuits. HoonSang Jin, Fabio Somenzi |
| 2005 | Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 William H. Joyner Jr., Grant Martin, Andrew B. Kahng |
| 2005 | Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints. Luis Alejandro Cortés, Petru Eles, Zebo Peng |
| 2005 | RADAR: RET-aware detailed routing using fast lithography simulations. Joydeep Mitra, Peng Yu, David Zhigang Pan |
| 2005 | RF MEMS in wireless architectures. Clark T.-C. Nguyen |
| 2005 | Race-condition-aware clock skew scheduling. Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu |
| 2005 | Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2005 | Response compaction with any number of unknowns using a new LFSR architecture. Erik H. Volkerink, Subhasish Mitra |
| 2005 | Robust gate sizing by geometric programming. Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar |
| 2005 | SEU tolerant device, circuit and processor design. William Heidergott |
| 2005 | Scalable trajectory methods for on-demand analog macromodel extraction. Saurabh K. Tiwary, Rob A. Rutenbar |
| 2005 | Secure scan: a design-for-test architecture for crypto chips. Bo Yang, Kaijie Wu, Ramesh Karri |
| 2005 | Segregation by primary phase factors: a full-wave algorithm for model order reduction. Thomas J. Klemas, Luca Daniel, Jacob K. White |
| 2005 | Should our power approach be current? Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski |
| 2005 | Sign bit reduction encoding for low power applications. Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi |
| 2005 | Simulation based deadlock analysis for system level designs. Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe |
| 2005 | Simulation models for side-channel information leaks. Kris Tiri, Ingrid Verbauwhede |
| 2005 | Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. Vinita Vasudevan |
| 2005 | Smart diagnostics for configurable processor verification. Sadik Ezer, Scott Johnson |
| 2005 | Spatially distributed 3D circuit models. Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter |
| 2005 | Statistical static timing analysis: how simple can we get? Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail |
| 2005 | Streamline verification process with formal property verification to meet highly compressed design cycle. Prosenjit Chatterjee |
| 2005 | StressTest: an automatic approach to test generation via activity monitors. Ilya Wagner, Valeria Bertacco, Todd M. Austin |
| 2005 | Structural search for RTL with predicate learning. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2005 | Structure preserving reduction of frequency-dependent interconnect. Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas |
| 2005 | Structured/platform ASIC apprentices: which platform will survive your board room? Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano |
| 2005 | System-level energy-efficient dynamic task scheduling. Jianli Zhuo, Chaitali Chakrabarti |
| 2005 | Systematic development of analog circuit structural macromodels through behavioral model decoupling. Ying Wei, Alex Doboli |
| 2005 | TCAM enabled on-chip logic minimization. Seraj Ahmad, Rabi N. Mahapatra |
| 2005 | Temperature-aware resource allocation and binding in high-level synthesis. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik |
| 2005 | Template-driven parasitic-aware optimization of analog integrated circuit layouts. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi |
| 2005 | The Titanic: what went wrong! Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse |
| 2005 | Timing-driven placement by grid-warping. Zhong Xiu, Rob A. Rutenbar |
| 2005 | Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. Feng Gao, John P. Hayes |
| 2005 | Towards scalable flow and context sensitive pointer analysis. Jianwen Zhu |
| 2005 | Trace-driven HW/SW cosimulation using virtual synchronization technique. Dohyung Kim, Youngmin Yi, Soonhoi Ha |
| 2005 | Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. Sven Heithecker, Rolf Ernst |
| 2005 | Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. Fei Su, Krishnendu Chakrabarty |
| 2005 | User-perceived latency driven voltage scaling for interactive applications. Le Yan, Lin Zhong, Niraj K. Jha |
| 2005 | VLIW: a case study of parallelism verification. Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy |
| 2005 | Variability and energy awareness: a microarchitecture-level perspective. Diana Marculescu, Emil Talpes |
| 2005 | Variation-tolerant circuits: circuit solutions and techniques. James W. Tschanz, Keith A. Bowman, Vivek De |
| 2005 | Variations-aware low-power design with voltage scaling. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm |
| 2005 | Wireless platforms: GOPS for cents and MilliWatts. Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt |
| 2005 | Word level predicate abstraction and refinement for verifying RTL verilog. Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke |