| 2000 | "Timing closure by design, " a high frequency microprocessor design methodology. Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia |
| 2000 | A Web-CAD methodology for IP-core analysis and simulation. Alessandro Fin, Franco Fummi |
| 2000 | A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums |
| 2000 | A codesign virtual machine for hierarchical, balanced hardware/software system modeling. JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas |
| 2000 | A current driven routing and verification methodology for analog applications. Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke |
| 2000 | A design of and design tools for a novel quantum dot based microprocessor. Michael T. Niemier, Michael J. Kontz, Peter M. Kogge |
| 2000 | A fast algorithm for context-aware buffer insertion. Ashok Jagannathan, Sung-Woo Hur, John Lillis |
| 2000 | A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. Junhyung Um, Taewhan Kim, C. L. Liu |
| 2000 | A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens |
| 2000 | A methodology for formal design of hardware control with application to cache coherence protocols. Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk |
| 2000 | A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif |
| 2000 | A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation. Baolin Yang, Joel R. Phillips |
| 2000 | A novel algorithm to extract two-node bridges. Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth |
| 2000 | A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits. Eileen You, Lakshminarasimh Varadadesikan, John Macdonald, Wieze Xie |
| 2000 | A rank-one update method for efficient processing of interconnect parasitics in timing analysis. H. Levy, W. Scott, Don MacMillen, Jacob White |
| 2000 | A realizable driving point model for on-chip interconnect with inductance. Chandramouli V. Kashyap, Byron Krauter |
| 2000 | A switch level fault simulation environment. Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff |
| 2000 | A system simulation framework. Peter van den Hamer, W. P. M. van der Linden, Peter Bingley, N. W. Schellingerhout |
| 2000 | An architecture-driven metric for simultaneous placement and global routing for FPGAs. Yao-Wen Chang, Yu-Tsang Chang |
| 2000 | An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder |
| 2000 | An instruction-level functionally-based energy estimation model for 32-bits microprocessors. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto |
| 2000 | Analysis of composition complexity and how to obtain smaller canonical graphs. Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu |
| 2000 | Application-specific memory management for embedded systems using software-controlled caches. Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas |
| 2000 | Area and search space control for technology mapping. Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten |
| 2000 | Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. Chung-Yang Huang, Kwang-Ting Cheng |
| 2000 | Automatic formal verification of DSP software. David W. Currie, Alan J. Hu, Sreeranga P. Rajan |
| 2000 | Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. Indradeep Ghosh, Masahiro Fujita |
| 2000 | B*-Trees: a new representation for non-slicing floorplans. Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu |
| 2000 | BDS: a BDD-based logic optimization system. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
| 2000 | Block placement with symmetry constraints based on the O-tree non-slicing representation. Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng |
| 2000 | Boolean satisfiability in electronic design automation. João P. Marques Silva, Karem A. Sakallah |
| 2000 | Bus encoding for low-power high-performance memory systems. Naehyuck Chang, Kwanho Kim, Jinsung Cho |
| 2000 | CGaAs PowerPC FXU. Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown |
| 2000 | COSY communication IP's. Jean-Yves Brunel, W. M. Kruijtzer, H. J. H. N. Kenter, Frédéric Pétrot, L. Pasquier, Erwin A. de Kock, W. J. M. Smits |
| 2000 | CYCLONE: automated design and layout of RF LC-oscillators. Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen |
| 2000 | Can recursive bisection alone produce routable placements? Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
| 2000 | Case studies: Chip design on the bleeding edge (panel session abstract). John M. Cohn, Rob A. Rutenbar, Steve J. Young, Chris Malachowsky, Luis Aldaz |
| 2000 | ClariNet: a noise analysis tool for deep submicron design. Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov |
| 2000 | Closing the gap between ASIC and custom: an ASIC perspective. David G. Chinnery, Kurt Keutzer |
| 2000 | Closing the gap between analog and digital. Khaled Saab, Naim Ben-Hamida, Bozena Kaminska |
| 2000 | Code compression for low power embedded system design. Haris Lekatsas, Jörg Henkel, Wayne H. Wolf |
| 2000 | Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
| 2000 | Compiling Esterel into sequential code. Stephen A. Edwards |
| 2000 | Convex delay models for transistor sizing. Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |
| 2000 | Critical path analysis using a dynamically bounded delay model. Soha Hassoun |
| 2000 | Current signature compression for IR-drop analysis. Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards |
| 2000 | Depth optimal incremental mapping for field programmable gate arrays. Jason Cong, Hui Huang |
| 2000 | Design closure (panel session): hope or hype? Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer |
| 2000 | Design of system-on-a-chip test access architectures under place-and-route and power constraints. Krishnendu Chakrabarty |
| 2000 | Designing systems-on-chip using cores. Reinaldo A. Bergamaschi, William R. Lee |
| 2000 | Distance driven finite state machine traversal. Andreas Hett, Christoph Scholl, Bernd Becker |
| 2000 | Domino logic synthesis minimizing crosstalk. Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang |
| 2000 | Dynamic noise analysis in precharge-evaluate circuits. Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De |
| 2000 | Dynamic power management of complex systems using generalized stochastic Petri nets. Qinru Qiu, Qing Wu, Massoud Pedram |
| 2000 | EDA meets.COM (panel session): how E-services will change the EDA business model. Jennifer Smith, Tom Quan, Andrew B. Kahng |
| 2000 | Efficient building block based RTL code generation from synchronous data flow graphs. Jens Horstmannshoff, Heinrich Meyr |
| 2000 | Efficient error detection, localization, and correction for FPGA-based debugging. John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak |
| 2000 | Efficient methods for embedded system design space exploration. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Efficient variable ordering using aBDD based sampling. Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita |
| 2000 | Embedded hardware and software self-testing methodologies for processor cores. Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
| 2000 | Embedded systems design in the new millennium (panel session). A. Richard Newton, Walden C. Rhines, Sünke Mehrgardt, Henry Samueli, Tudor Brown |
| 2000 | Embedded systems education (panel abstract). Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne H. Wolf |
| 2000 | Emerging companies - acquiring minds want to know (panel session). Dan Schweikert, Joseph B. Costello, Rajeev Madhavan, Y. C. Pati, Judy Owen, Steve Carlson, Moshe Gavrielov |
| 2000 | Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources. Janet Meiling Wang, Tuyen V. Nguyen |
| 2000 | Fast methods for extraction and sparsification of substrate coupling. Joe Kanapka, Joel R. Phillips, Jacob White |
| 2000 | Fast post-placement rewiring using easily detectable functional symmetries. Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska |
| 2000 | Fast power grid simulation. Sani R. Nassif, Joseph N. Kozhaya |
| 2000 | Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. Ching-Han Tsai, Sung-Mo Kang |
| 2000 | Fingerprinting intellectual property using constraint-addition. Gang Qu, Miodrag Potkonjak |
| 2000 | Floorplan sizing by linear programming approximation. Pinghong Chen, Ernest S. Kuh |
| 2000 | Forensic engineering techniques for VLSI CAD tools. Darko Kirovski, David T. Liu, Jennifer L. Wong, Miodrag Potkonjak |
| 2000 | Formal verification of an IBM CoreConnect processor local bus arbiter core. Amit Goel, William R. Lee |
| 2000 | Formal verification of iterative algorithms in microprocessors. Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger |
| 2000 | Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. Miroslav N. Velev, Randal E. Bryant |
| 2000 | Function-level power estimation methodology for microprocessors. Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak |
| 2000 | Future systems-on-chip: software of hardware design? (panel session). Brian Dipert, Danesh Tavana, Barry K. Britton, Bill Harris, Bob Boderson, Chris Rowen |
| 2000 | GTX: the MARCO GSRC technology extrapolation system. Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester |
| 2000 | Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization. Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima, Teruo Higashino, Kenichi Taniguchi |
| 2000 | Hardware-software co-design of embedded reconfigurable architectures. Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood |
| 2000 | Hardware/software IP protection. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini |
| 2000 | Hierarchical analysis of power distribution networks. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw |
| 2000 | High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. Vince E. Boros, Aleksandar D. Rakic, Sri Parameswaran |
| 2000 | High-level simulation of substrate noise generation including power supply noise coupling. Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens |
| 2000 | Impact of interconnect variations on the clock skew of a gigahertz microprocessor. Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2000 | Improved fault diagnosis in scan-based BIST via superposition. Ismet Bayraktaroglu, Alex Orailoglu |
| 2000 | Influence of compiler optimizations on system power. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye |
| 2000 | Interactive co-design of high throughput embedded multimedia. Thierry J.-F. Omnés, Thierry Franzetti, Francky Catthoor |
| 2000 | Interconnect testing in cluster-based FPGA architectures. Ian G. Harris, Russell Tessier |
| 2000 | Large-scale capacitance calculation. Sharad Kapur, David E. Long |
| 2000 | Lazy symbolic model checking. Jin Yang, Andreas Tiemeyer |
| 2000 | Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow |
| 2000 | METRICS: a system architecture for design process optimization. Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges |
| 2000 | MINFLOTRANSIT: min-cost flow based transistor sizing tool. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
| 2000 | MOSFET modeling and circuit design: re-establishing a lost connection (tutorial). Daniel Foty, David M. Binkley |
| 2000 | Macro-driven circuit design methodology for high-performance datapaths. Mahadevamurty Nemani, Vivek Tiwari |
| 2000 | Maze routing with buffer insertion and wiresizing. Minghorng Lai, D. F. Wong |
| 2000 | Memory aware compilation through accurate timing extraction. Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
| 2000 | Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. Ruiqi Tian, D. F. Wong, Robert Boone |
| 2000 | Modeling and simulation of real defects using fuzzy logic. Amir Attarha, Mehrdad Nourani, Caro Lucas |
| 2000 | MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh |
| 2000 | Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. Tao Pi, Chuanjin Richard Shi |
| 2000 | Multiple Si layer ICs: motivation, performance analysis, and design implications. Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat |
| 2000 | Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor. Jen-Tien Yen, Qichao Richard Yin |
| 2000 | On diagnosis of pattern-dependent delay faults. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | On lower bounds for scheduling problems in high-level synthesis. M. Narasimhan, J. Ramanujam |
| 2000 | On switch factor based analysis of coupled Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
| 2000 | On-chip inductance modeling and analysis. Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw |
| 2000 | Operating system based software generation for systems-on-chip. Dirk Desmet, Diederik Verkest, Hugo De Man |
| 2000 | Optimal RF design using smart evolutionary algorithms. Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen |
| 2000 | Optimal low power X OR gate decomposition. Hai Zhou, D. F. Wong |
| 2000 | Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. Zhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha |
| 2000 | Optimizing sequential verification by retiming transformations. Gianpiero Cabodi, Stefano Quer, Fabio Somenzi |
| 2000 | Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh |
| 2000 | Passive model order reduction of multiport distributed interconnects. Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar |
| 2000 | Performance analysis and optimization of latency insensitive systems. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Performance driven multi-level and multiway partitioning with retiming. Jason Cong, Sung Kyu Lim, Chang Wu |
| 2000 | Power analysis of embedded operating systems. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha |
| 2000 | Power minimization derived from architectural-usage of VLIW processors. Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga |
| 2000 | Power minimization using control generated clocks. M. Srikanth Rao, S. K. Nandy |
| 2000 | Practical iterated fill synthesis for CMP uniformity. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2000 | Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments. Bernard N. Sheehan |
| 2000 | Predicting performance potential of modern DSPs. Naji Ghazal, A. Richard Newton, Jan M. Rabaey |
| 2000 | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. Giovanni De Micheli |
| 2000 | Projection frameworks for model reduction of weakly nonlinear systems. Joel R. Phillips |
| 2000 | Reliable verification using symbolic simulation with scalar values. Chris Wilson, David L. Dill |
| 2000 | Removing user specified false paths from timing graphs. David T. Blaauw, Rajendran Panda, Abhijit Das |
| 2000 | Routing tree construction under fixed buffer locations. Jason Cong, Xin Yuan |
| 2000 | Run-time voltage hopping for low-power real-time systems. Seongsoo Lee, Takayasu Sakurai |
| 2000 | Schedulability-driven performance analysis of multiple mode embedded real-time systems. Youngsoo Shin, Daehong Kim, Kiyoung Choi |
| 2000 | Self-test methodology for at-speed test of crosstalk in chip interconnects. Xiaoliang Bai, Sujit Dey, Janusz Rajski |
| 2000 | Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction. Jinsong Zhao |
| 2000 | Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology. Kenneth L. Shepard, Dae-Jin Kim |
| 2000 | Survival strategies for mixed-signal systems-on-chip (panel session). Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy |
| 2000 | Symbolic guided search for CTL model checking. Roderick Bloem, Kavita Ravi, Fabio Somenzi |
| 2000 | Symbolic timing simulation using cluster scheduling. Clayton B. McDonald, Randal E. Bryant |
| 2000 | Synthesis and optimization of coordination controllers for distributed embedded systems. Pai H. Chou, Gaetano Borriello |
| 2000 | Synthesis of application-specific memories for power optimization in embedded systems. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2000 | Synthesis-for-testability of controller-datapath pairs that use gated clocks. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
| 2000 | System chip test: how will it impact your design? Yervant Zorian, Erik Jan Marinissen |
| 2000 | System design of Athanassios Boulis, Mani B. Srivastava |
| 2000 | System-level data format exploration for dynamically allocated data structures. Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani |
| 2000 | Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen |
| 2000 | TACO: timing analysis with coupling. Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi |
| 2000 | Task generation and compile-time scheduling for mixed data-control embedded software. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Task scheduling with RT constraints. Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin |
| 2000 | Test challenges for deep sub-micron technologies. Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy |
| 2000 | The design and use of simplepower: a cycle-accurate energy estimation tool. Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
| 2000 | The future of system design languages (panel session). Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia |
| 2000 | The role of custom design in ASIC Chips. William J. Dally, Andrew Chang |
| 2000 | The use of carry-save representation in joint module selection and retiming. Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr. |
| 2000 | Timing-driven placement based on partitioning with dynamic cut-net control. Shih-Lian T. Ou, Massoud Pedram |
| 2000 | To split or to conjoin: the question in image computation. In-Ho Moon, James H. Kukula, Kavita Ravi, Fabio Somenzi |
| 2000 | Unifying behavioral synthesis and physical design. William E. Dougherty, Donald E. Thomas |
| 2000 | Universal fault simulation using fault tuples. Kumar N. Dwarakanath, Ronald D. Blanton |
| 2000 | Using general-purpose programming languages for FPGA design. Brad L. Hutchings, Brent E. Nelson |
| 2000 | Verification of configurable processor cores. Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas |
| 2000 | Watermarking while preserving the critical path. Seapahn Meguerdichian, Miodrag Potkonjak |
| 2000 | Wave-steering one-hot encoded FSMs. Luca Macchiarulo, Malgorzata Marek-Sadowska |
| 2000 | Web-based frameworks to enable CAD RD (abstract). Olivier Coudert, Igor L. Markov, Christoph Meinel, Ellen Sentovich |
| 2000 | When bad things happen to good chips (panel session). N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang |
| 2000 | YAPI: application modeling for signal processing systems. Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink |