DAC A*

126 papers

YearTitle / Authors
1984A VLSI FSM design system.
M. J. Meyer, Prathima Agrawal, R. G. Pfister
1984A VLSI design methodology based on parametric macro cells.
R. A. Kriete, R. K. Nettleton
1984A branch and bound algorithm for optimal pla folding.
James L. Lewandowski, C. L. Liu
1984A declarative design approach for combining macrocells by directed placement and constructive routing.
C. L. Wardle, Charles R. Watson, C. A. Wilson, J. Craig Mudge, Bradley J. Nelson
1984A designing system for multi-family housing.
Barry Jackson
1984A formal design verification system based on an automated reasoning system.
Anthony S. Wojcik, Joseph Kljaich Jr., Nagendra C. E. Srinivas
1984A gate level model for CMOS combinational logic circuits with application to fault detection.
Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain
1984A general methodology for synthesis and verification of register-transfer designs.
Alice C. Parker, Fadi J. Kurdahi, Mitch J. Mlinar
1984A global routing algorithm for general cells.
Gary W. Clow
1984A hiererachical, error-tolerant compactor.
Christopher Kingsley
1984A high level synthesis tool for MOS chip design.
Jean-Pierre Dussault, Chi-Chang Liaw, Michael M. Tong
1984A knowledge based approach to VLSI CAD the redesign system.
Louis I. Steinberg, Tom M. Mitchell
1984A method for IC layout verification.
Ola A. Marvik
1984A model for hardware description and verification.
George J. Milne
1984A model for non interpreted structures of logical systems.
R. Alali, C. Durante, J. J. Mercier
1984A model for university, industry and government cooperation.
Lawrence Snyder
1984A multiprocessor implementation of relaxation-based electrical circuit simulation.
Jeffrey T. Deutsch, A. Richard Newton
1984A standard cell initial placement strategy.
Bill D. Richard
1984A switchbox router with obstacle avoidance.
Gordon T. Hamachi, John K. Ousterhout
1984A symbolic functional description language.
Gotaro Odawara, Jun Sato, Masahiro Tomita
1984A symbolic-interconnect router for custom IC design.
Charles H. Ng
1984A systolic design rule checker.
Rajiv Kane, Sartaj Sahni
1984A technology independent MOS multiplier generator.
Kung-Chao Chu, Ramautar Sharma
1984A technology independent block extraction algorithm.
F. Luellau, T. Hoepken, Erich Barke
1984A unified CAD system for electronic design.
John C. Foster
1984A wire routing scheme for double-layer cell arrays.
Guy Dupenloup
1984ADL: An algorithmic design language for integrated circuit synthesis.
W. H. Evans, Jean-Claude Ballegeer, Nguyen H. Duyet
1984ARIES: A workstation based, schematic driven system for circuit design.
William H. Kao, Mohammad H. Movahed-Ezazi, Mark L. Sabiers
1984Amoeba: A symbolic VLSI layout system.
Mikhail Lotvin, Belinda Juran, Reeni Goldin
1984An MOS digital network model on a modified thevenin equivalent for logic simulation.
Tsuyoshi Takahashi, Satoshi Kojima, Osamu Yamashiro, Kazuhiko Eguchi, Hideki Fukuda
1984An algorithm for building rectangular floor-plans.
Sany M. Leinwand, Yen-Tai Lai
1984An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits.
Krzysztof Kozminski, Edwin Kinnen
1984An approach to the testing of microprocessors.
Mark G. Karpovsky, Rodney Van Meter
1984An architecture for application of artificial intelligence to design.
John R. Dixon, Melvin K. Simmons, Paul R. Cohen
1984An automated system for testing LSI memory chips.
H. D. Schnurmann, L. J. Vidunas, R. M. Peters
1984An efficient channel router.
Takeshi Yoshimura
1984An electronic design interchange format.
John D. Crawford
1984An experimental MOS fault simulation program CSASIM.
Masato Kawai, John P. Hayes
1984An integrated design for testability and automatic test pattern generation system: An overview.
Erwin Trischler
1984An interactive electrical graph extractor.
J. L. Kors, M. Israel
1984Basic turorial layout tools - what really is there.
R. Smith
1984Block description language (BDL): A structural description language.
Eric Slutz, Glen Okita, Jeanne Wiseman
1984Cell compilation with constraints.
Chidchanok Lursinsap, Daniel Gajski
1984Chip layout optimization using critical path weighting.
Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel
1984Chip partitioning aid: A design technique for partitionability and testability in VLSI.
Subrata Dasgupta, M. C. Graf, Robert A. Rasmussen, Ron G. Walther, Tom W. Williams
1984Combine and top down block placement algorithm for hierarchical logic VLSI layout.
Tokinori Kozawa, Chihei Miura, Hidekazu Terai
1984Commercial gate array physical design automation packages.
Frederick Hinchliffe II
1984Computer aided design (CAD) using logic programming.
Paul W. Horstmann, Edward P. Stabler
1984Computer aided minimization procedure for boolean functions.
Nripendra N. Biswas
1984Computervision's direction in workstation technology.
Guy D. Haas
1984Deadlock analysis in the design of data-flow circuits.
Chu S. Jhon, Robert M. Keller
1984Delay and power optimization in VLSI circuits.
Lance A. Glasser, Lennox Hoyte
1984Design transaction management.
Randy H. Katz, Shlomo Weiss
1984EXCL: A circuit extractor for IC designs.
Steven Paul McCormick
1984Efficient implementation of experimental design systems.
George D. M. Ross
1984Emerald: A bus style designer.
Chia-Jeng Tseng, Daniel P. Siewiorek
1984Engineering design aspects.
Herbert Y. Chang, Richard N. Talmadge
1984Ergonomic studies in computer aided design.
Gerard H. van der Heiden, Etienne Grandjean
1984Extending the relational database data model for design applications.
Martin Hardwick
1984Functional design verification by multi-level simulation.
Kit Tham, Rob Willoner, David Wimp
1984Functional testing techniques for digital LSI/VLSI systems.
Stephen Y. H. Su, Tonysheng Lin
1984Functional verification of memory circuits from mask artwork data.
Masahiko Kawamura, Haruo Takagi, Kanji Hirabayashi
1984GALA - an automatic layout system for high density CMOS gate arrays.
Bou Nin Tien, B. S. Ting, J. Cheam, Kenneth S. K. Chow, Scott C. Evans
1984HARPA: A hierarchical multi-level hardware description language.
Pedro Veiga, Mário Lança
1984Hardware accelerators in the design automation environment.
Ram Banin
1984Hierarchical layout verification.
Todd J. Wagner
1984IDA: Interconnect delay analysis for integrated circuits.
Aart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle
1984IGES as an interchange format for integrated circuit design.
Curtis H. Parks
1984Initial placement of gate arrays using least-squares methods.
John P. Blanks
1984Interactive compaction router for VLSI layout.
Hajimu Mori
1984Introduction to the SRC design sciences program.
Ralph K. Cavin III
1984MGX: An integrated symbolic layout system for VLSI.
Masaru Ozaki, Miho Watanabe, Morio Kakinuma, Mikio Ikeda, Koji Sato
1984MINUPROX - an advanced proximity correction technique for the IBM EL-2 electron beam tool.
W. J. Guillaume, A. Kurylo
1984Magic's incremental design-rule checker.
George S. Taylor, John K. Ousterhout
1984Magic: A VLSI layout system.
John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor
1984Managing a large volume of design/manufacturing/test data in a chip and module factory.
Vincent J. Freund Jr.
1984Methodology for compiler generated silicon structures.
Antonio Martínez, Scott Nance
1984Micro-computer oriented algorithms for delay evaluation of MOS gates.
Daniel Etiemble, V. Adeline, Nguyen H. Duyet, J. C. Ballegeer
1984Microprocessor synthesis.
Vijay K. Raj, Barry M. Pangrle, Daniel D. Gajski
1984Module design verification system.
Lloyd Wilkins
1984Module positioning algorithms for rectilinear macrocell assemblies.
Jack A. Hudson, John A. Wisniewski, Randy C. Peters
1984On the relation between wire length distributions and placement of logic on master slice ICs.
Sarma Sastry, Alice C. Parker
1984Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler.
Andrzej Wieclawski, Marek A. Perkowski
1984Optimization techniques for two-dimensional placement.
Lev A. Markov, Jeffrey R. Fox, John H. Blank
1984Oracle - a simulator for Bipolar and MOS IC design.
Manuel A. d'Abreu, K. L. Cheong, C. T. Flanagan
1984Parameterized random testing.
Karl J. Lieberherr
1984Performance of algorithms for initial placement.
Michael Palczewski
1984Performance verification of circuits.
Jerry Mar, You-Pang Wei
1984Phled45: An enhanced version of caesar supporting 45° geometries.
Ann R. Lanfri
1984Physical design and manufacturing information aspects aspects of the AT & T bell laboratories CAD system.
Charles W. Rosenthal
1984Plowing: Interactive stretching and compaction in magic.
Walter S. Scott, John K. Ousterhout
1984Polaris: Polarity propagation algorithm for combinational logic synthesis.
T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, Koichiro Ishihara
1984Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984
Patricia H. Lambert, Hillel Ofek, Lawrence A. O'Neill, Pat O. Pistilli, Paul Losleben, J. Daniel Nash, Dennis W. Shaklee, Bryan T. Preas, Harvey N. Lerman
1984STAFAN: An alternative to fault simulation.
Sunil K. Jain, Vishwani D. Agrawal
1984Silicon compilers and expert systems for VLSI.
Daniel D. Gajski
1984Some consideration on the data model of geometric data bases.
Jinglun Zhang, Renhua Wang
1984Spider, a chip planner for ISL technology.
Prakash Rao, R. Ramnarayan, Gerhard Zimmermann
1984Studying the mouse for CAD systems.
Lynne A. Price
1984Switch-level delay models for digital MOS VLSI.
John K. Ousterhout
1984THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator.
Mahesh H. Doshi, Roderick B. Sullivan, Donald M. Schuler
1984Taking into account asynchronous signals in functional test of complex circuits.
Catherine Bellon, Raoul Velazco
1984Test generation for LSI: A case study.
Magdy S. Abadir, Hassan K. Reghbati
1984The CRITTER system: Automated critiquing of digital circuit designs.
Van E. Kelly
1984The Intel design automation system.
Stephen Nachtsheim
1984The VHSIC hardware description language (VHDL) program.
Al Dewey
1984The channel expansion problem in layout design.
Rachel R. Chen, Yoji Kajitani
1984The engineering design environment.
Kirk Sherhart, Mark Vershel, Judy Owen
1984The icewater language and interpreter.
Patrick A. D. Powell, Mohamed I. Elmasry
1984The mimola design system: Tools for the design of digital processors.
Peter Marwedel
1984The rectangle placement language.
John Alan Roach
1984The scan line approach to design rules checking: Computational experiences.
P. T. Chapman, K. Clark Jr.
1984The second generation motis mixed-mode simulator.
Chin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam
1984The semi-automatic generation of processing element control paths for highly parallel machines.
Theodore Sabety, David Elliot Shaw, Brian Mathies
1984The semi-custom revolution: How to thrive or survive.
Anthony Zingale
1984The structure and operation of a relational database system in a cell-oriented integrated circuit design system.
Lee A. Hollaar, Brent E. Nelson, Tony M. Carter, Raymond A. Lorie
1984Topological routing of multi-bit data buses.
G. Persky, L. V. Tran
1984Towards a standard hardware description language.
Karl J. Lieberherr
1984Tutorial - mechanical workstation software computer aided engineering in the mechanical design process.
J. Scott
1984UTMC's LSI CAD system - highland.
K. Anderson, R. Powell
1984Ultimate: A hardware logic simulation engine.
M. E. Glazier, Anthony P. Ambler
1984Uniform support for information handling and problem solving required by the VLSI design process.
V. Ashok, Walter Lee McKnight, Jayashree Ramanathan
1984Users view.
John Colton, Frank E. Swiatek, D. H. Edwards
1984VLSI test expertise system using a control flow model.
Gabriele Saucier, Catherine Bellon
1984VTIcompose - a powerful graphical chip assembly tool.
Stephen Trimberger
1984Workshop introduction to gate array placement and routing packages.
Frederick Hinchliffe II, R. V. Alessi, J. Bunik, P. Catapano, M. Kubota, R. H. Dean, E. Dorsey, M. Leddell
1984Workshop the semi-custom revolution: How to thrive or survive.
A. Zingale, F. Kohn, F. Lynch, D. Kalbarsh