DAC A*

136 papers

YearTitle / Authors
1983"Minimizing PWB NC drilling".
John D. Litke
1983A data structure for MOS circuits.
Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose
1983A design verification methodology based on concurrent simulation and clock suppression.
Ernst G. Ulrich
1983A graphical tool for conceptual design of data base applications.
Carlo Batini, C. Costa
1983A layout verification system for analog bipolar integrated circuits.
Erich Barke
1983A logic design front-end for improved engineering productivity.
Frank Rubin, Paul W. Horstmann
1983A method of automatic data path synthesis.
Charles Y. Hitchcock III, Donald E. Thomas
1983A module interchange placement machine.
Alexander Iosupovicz, Clarence King, Melvin A. Breuer
1983A multiple media delay simulator for MOS LSI circuits.
Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara
1983A new channel routing problem.
Hon Wai Leong, C. L. Liu
1983A new integrated system for PLA testing and verification.
Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
1983A new statistical model for gate array routing.
Abbas El Gamal, Zahir A. Syed
1983A placement algorithm for array processors.
Dah-Juh Chyan, Melvin A. Breuer
1983A topology for semicustom array-structured LSI devices, and their automatic customisation.
P. Jennings
1983A vertically integrated VLSI design environment.
Jonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste
1983ACE: A Circuit Extractor.
Anoop Gupta
1983APSS: An automatic PLA synthesis system.
M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller
1983An algebra for logic strength simulation.
Peter Flake, Philip Moorby, Gerry Musgrave
1983An algorithm to compact a VLSI symbolic layout with mixed constraints.
Yuh-Zen Liao, Chak-Kuen Wong
1983An improved switch-level simulator for MOS circuits.
Vijaya Ramachandran
1983An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM).
John A. Board Jr., Peter N. Marinos
1983An over-cell gate array channel router.
Howard E. Krohn
1983An overview of the design and verification subsystem of the Engineering Design System.
Larry N. Dunn
1983Aquarius: Logic simulation on an Engineering Workstation.
Andrew Sangster, John Monahan
1983Automatic batch processing in multilayer ceramic metallization.
Neil DalCero
1983Automatic layout for gate arrays with one layer of metal.
Peter Robinson
1983Automatic placement algorithms for high packing density V L S I.
Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno
1983Automatic routing of double layer gate arrays using a moving cursor.
B. D. Prazic, M. A. Bozier
1983Automating mask layout and specification panel session.
Robert Brian Cutler
1983BIMOS, an MOS oriented multi-level logic simulator.
Piet Stevens, Guido Arnout
1983Behavioral level transformation in the CMU-DA system.
Robert A. Walker, Donald E. Thomas
1983Binary Decision Diagrams: From abstract representations to physical implementations.
Jose S. Metos, John V. Oldfield
1983Bounds on the saved area ratio due to PLA folding.
Wentai Liu, Daniel E. Atkins
1983CAD/CAM - the foundation for Computer Integrated Manufacturing.
Richard L. Simon
1983CAF: A computer-assisted floorplanning tool.
André Leblond
1983Central DA and its role: An executive view.
Robert J. Camoin
1983Chip assemblers: Concepts and capabilities.
Randy H. Katz, Shlomo Weiss
1983Classes of diagnostic tests.
Charles Paulson
1983Computer Aided Programming.
Paul Bassett
1983Computer Aided Software Engineering (CASE).
F. W. Day
1983Computer Design Language - Version Munich (CDLM) a modern multi-level language.
Winfried Hahn
1983Computer-aided partitioning of behavioral hardware descriptions.
Michael C. McFarland
1983Consistency checking for MOS/VLSI circuits.
Ning-Sang Chang, Ravi Apte
1983Critical path tracing - an alternative to fault simulation.
Miron Abramovici, Prem R. Menon, David T. Miller
1983Design For Test Calculus: An algorithm for DFT rules checking.
Dilip K. Bhavsar
1983Design aids for the simulation of bipolar gate arrays.
Patrick Kozak, Ajoy K. Bose, A. Gupta
1983Design automation - lessons of the past, challenges for the future.
John S. Mayo
1983Design through transformation.
J. B. Bendas
1983Design/synthesis workshop session.
J. Robert Logan
1983Diagnosis of TCM failures in the IBM 3081 Processor complex.
Nandakumar N. Tendolkar
1983Edisim and Edicap: Graphical simulator interfaces.
Dwight D. Hill
1983Engineering Workstations: Tools or toys?
Steve Sapiro
1983Experiments with the SLIM Circuit Compactor.
Ralph McGarity, Daniel P. Siewiorek
1983Facet: A procedure for the automated synthesis of digital systems.
Chia-Jeng Tseng, Daniel P. Siewiorek
1983Formal design verification of digital systems.
Anthony S. Wojcik
1983Formal verification of a real-time hardware design.
Zerksis D. Umrigar, Vijay Pitchumani
1983Functional models for VLSI design.
Roy L. Druian
1983Functional simulation shortens the development cycle of a new computer.
Raymond Cheng, Brian Griffin, Kun Katsumata, John Welsh
1983Functional testing of digital systems.
Kwok-Woon Lai, Daniel P. Siewiorek
1983General river routing algorithm.
Chi-Ping Hsu
1983Graph-optimization techniques for IC layout and compaction.
Gershon Kedem, Hiroyuki Watanabe
1983HAL: A block level HArdware Logic simulator.
Tohru Sasaki, Nobuhiko Koike, Kenji Ohmori, Kyoji Tomita
1983HEX: An instruction-driven approach to feature extraction.
Mark Hofmann, Ulrich Lauther
1983HOPLA-PLA optimization and synthesis.
Shmuel Wimer, N. Sharfman
1983Heuristics for the Circuit Realization Problem.
James Cohoon, Sartaj Sahni
1983Hierarchical channel router.
Michael Burstein, Richard N. Pelavin
1983Hierarchical circuit extraction with detailed parasitic capacitance.
Gary M. Tarolli, William J. Herman
1983IBM FSD VLSI chip design methodology.
K. Ahdoot, Rita R. Alvarodiaz, L. Crawley
1983ILS - interactive logic simulator.
Gregory D. Jordan, Brij B. Popli
1983Importance of device independence to the CADCAM industry.
James R. Warner
1983Improved compaction by minimized length of wires.
Werner L. Schiele
1983Incorporating the human factor in color CAD systems.
Francine S. Frome
1983Integrated computer aided design, documentation and manufacturing system for PCB electronics.
Mikko Tervonen, Hannu Lehikoinen, Timo Mukari
1983Integration of solid modeling and data base management for CAD/CAM.
Yung-Chia Lee, King-Sun Fu
1983Internal connection problem in large optimized PLAs.
Samuel Chuquillanqui
1983Laying the power and ground wires on a VLSI chip.
Anderew S. Moulton
1983Linear ordering and application to placement.
Sungho Kang
1983MACH : a high-hitting pattern checker for VLSI mask data.
Akira Tsukizoe, Jun'ya Sakemi, Tokinori Kozawa, Hiroshi Fukuda
1983Measured performance of a programmed implementation of the subscripted D-Algorithm.
C. Benmehrez, John F. McDonald
1983Microprocessor systems modeling with MODLAN.
Adam Pawlak
1983Microprocessor systems modeling with MODLAN.
Adam Pawlak
1983N.mPc: A retrospective.
Charles W. Rose, Greg M. Ordy, Frederic I. Parke
1983On fault detection in CMOS logic networks.
Kuang-Wei Chiang, Zvonko G. Vranesic
1983Optimisation of global routing for the UK5000 gate array by iteration.
C. O. Newton, Patricia A. Young
1983Optimum reduction of programmable logic array.
T. C. Hu, Yue-Sun Kuo
1983PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays.
Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli
1983PRONTO: Quick PLA product reduction.
Jorge Martínez-Carballido, V. Michael Powers
1983Partitioning and placement technique for bus-structured PWB.
Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu
1983Path delay analysis for hierarchical building block layout system.
Eiji Tamura, Kimihiro Ogawa, Toshio Nakano
1983Petri Net based search directing heuristics for test generation.
E. Kofi Vida-Torku, Beverly Messick Huey
1983Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool.
Robert N. Mayo, John K. Ousterhout
1983Placement algorithms for custom VLSI.
Kenneth J. Supowit, Eric A. Slutz
1983Placement of circuit modules using a graph space approach.
Kunio Fukunaga, Shoichiro Yamada, Harold S. Stone, Tamotsu Kasai
1983Placement of irregular circuit elements on non-uniform gate arrays.
Harold Kirk, P. D. Crowhurst, J. A. Skingley, J. Dan Bowman, G. L. Taylor
1983Position paper role of technology design rules in Design Automation.
Gayla J. Von Ehr
1983Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983
Charles E. Radke
1983Program visualization: Graphics support for software development.
David Kramlich, Gretchen P. Brown, Richard T. Carling, Christopher F. Herot
1983Programmimg languages for hardware description.
Peter Robinson, Jeremy Dion
1983Quality level and fault coverage for multichip modules.
E. Kofi Vida-Torku, Charles E. Radke
1983Reducing channel density in standard cell layout.
Kenneth J. Supowit
1983Robots in design (Panel Discussion).
Ernest L. Hall
1983Routing method for VLSI design using irregular cells.
Hans-Jürgen Rothermel, Dieter A. Mlynski
1983Simplification of CNC programming for PWB routing.
J. Drier
1983Simulating pass transistor circuits using logic simulation machines.
Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo
1983Software architecture for the implementation of a Computer-Aided Engineering system.
Charles L. Leath, Steven J. Ollanik
1983Solid model in geometric modelling system: HICAD.
Shinji Tokumasu, Yoshio Kunitomo, Yoshimi Ohta, Shigeru Yamamoto, Norihiro Nakajima
1983Some Computer Aided Engineering System design principles.
Henry L. Nattrass, Glen K. Okita
1983Space efficient algorithms for VLSI artwork analysis.
Thomas G. Szymanski, Christopher J. Van Wyk
1983Statistical techniques of timing verification.
James H. Shelly, David R. Tryon
1983Structured design verification: Function and timing.
C. J. Rimkus, Michael R. Wayne, D. D. Cheng, F. J. Magistro
1983Symbolic Parasitic Extractor for Circuit Simulation (SPECS).
J. D. Bastian, M. Ellement, Priscilla J. Fowler, C. E. Huang, Lawrence P. McNamee
1983Technology design rules - a user's perspective.
Thomas R. Reinke
1983Technology rules- the other side of technology dependent code.
Melvin F. Heilweil
1983Technology-independent circuit layout.
Robert J. Smith
1983Test generation for MOS circuits using D-algorithm.
Sunil K. Jain, Vishwani D. Agrawal
1983Test generation for scan design circuits with tri-state modules and bidirectional terminals.
Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara
1983Test strategy for microprocessers.
Sunil K. Jain, Alfred K. Susskind
1983Testing for bridging faults (shorts) in CMOS circuits.
John M. Acken
1983The IC Module Compiler, a VLSI system design aid.
N. J. Elias, Arthur W. Wetzel
1983The N.2 System.
Greg M. Ordy, Charles W. Rose
1983The Transfer of University Software for Industry Use.
Rossane Wyleczuk, Lynn Meyer, Gigi Babcock
1983The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test.
J. R. Grierson, B. Cosgrove, Daniel Richert, R. E. Halliwell, Harold Kirk, John C. Knight, John A. McLean, J. M. McGrail, C. O. Newton
1983The VLSI Design Automation Assistant: Prototype system.
Thaddeus J. Kowalski, Donald E. Thomas
1983The effect of register-transfer design tradeoffs on chip area and performance.
John J. Granacki, Alice C. Parker
1983The relational data model for CAD(Tutorial/Panel/Workshop): Close encounters of the third normal form.
Stanley Wong
1983Timing analysis for nMOS VLSI.
Norman P. Jouppi
1983Total stuct-at-fault testing by circuit transformation.
Andrea S. LaPaugh, Richard J. Lipton
1983Tutorial - Group Technology.
Hriday R. Prasad
1983Tutorial: The relational data model for Design Automation.
Mark N. Haynie
1983UCAD: Building Design Automation with general purpose software tools on UNIX.
James H. Tomkinson
1983UNIGRAFIX.
Carlo H. Séquin, Paul S. Strauss
1983VERDI: A computer aided design system for development and city planning.
M. Bouyat, H. Botta, J. C. Vignat
1983VGAUA: The Variable Geometry Automated Universal Array layout System.
David C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas
1983VHSIC hardware description (VHDL) development program.
Al Dewey
1983Workshop - technology design rules for design automation.
Ronald Waxman, Melvin F. Heilweil, Tom Reinke, Robert J. Smith, Gayla J. Von Ehr
1983Zeus: A hardware description language for VLSI.
Karl J. Lieberherr, Svend E. Knudsen