CHES A

32 papers

YearTitle / Authors
2007A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter.
Joshua Jaffe
2007A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations.
Andrey Bogdanov, Thomas Eisenbarth, Andy Rupp
2007AES Encryption Implementation and Analysis on Commodity Graphics Processing Units.
Owen Harrison, John Waldron
2007Arithmetic Operators for Pairing-Based Cryptography.
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
2007CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method.
Tetsuya Izu, Jun Kogure, Takeshi Shimoyama
2007Collision Attacks on AES-Based MAC: Alpha-MAC.
Alex Biryukov, Andrey Bogdanov, Dmitry Khovratovich, Timo Kasper
2007Collision Search for Elliptic Curve Discrete Logarithm over GF(2
Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater
2007Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings
Pascal Paillier, Ingrid Verbauwhede
2007DPA-Resistance Without Routing Constraints?
Benedikt Gierlichs
2007Differential Behavioral Analysis.
Bruno Robisson, Pascal Manet
2007Evaluation of the Masked Logic Style MDPL on a Prototype Chip.
Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard
2007FPGA Design of Self-certified Signature Verification on Koblitz Curves.
Kimmo U. Järvinen, Juha Forsten, Jorma Skyttä
2007FPGA Intrinsic PUFs and Their Use for IP Protection.
Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls
2007Gaussian Mixture Models for Higher-Order Side Channel Analysis.
Kerstin Lemke-Rust, Christof Paar
2007High-Speed True Random Number Generation with Logic Gates Only.
Markus Dichtl, Jovan Dj. Golic
2007Highly Regular Right-to-Left Algorithms for Scalar Multiplication.
Marc Joye
2007How to Maximize the Potential of FPGA Resources for Modular Exponentiation.
Daisuke Suzuki
2007Information Theoretic Evaluation of Side-Channel Resistant Logic Styles.
François Macé, François-Xavier Standaert, Jean-Jacques Quisquater
2007MAME: A Compression Function with Reduced Hardware Requirements.
Hirotaka Yoshida, Dai Watanabe, Katsuyuki Okeya, Jun Kitahara, Hongjun Wu, Özgül Küçük, Bart Preneel
2007Masking and Dual-Rail Logic Don't Add Up.
Patrick Schaumont, Kris Tiri
2007Multi-gigabit GCM-AES Architecture Optimized for FPGAs.
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli
2007On the Implementation of a Fast Prime Generation Algorithm.
Christophe Clavier, Jean-Sébastien Coron
2007On the Power of Bitslice Implementation on Intel Core2 Processor.
Mitsuru Matsui, Junko Nakajima
2007PRESENT: An Ultra-Lightweight Block Cipher.
Andrey Bogdanov, Lars R. Knudsen, Gregor Leander, Christof Paar, Axel Poschmann, Matthew J. B. Robshaw, Yannick Seurin, C. Vikkelsoe
2007Power Analysis Resistant AES Implementation with Instruction Set Extensions.
Stefan Tillich, Johann Großschädl
2007Power and EM Attacks on Passive 13.56 MHz RFID Devices.
Michael Hutter, Stefan Mangard, Martin Feldhofer
2007RF-DNA: Radio-Frequency Certificates of Authenticity.
Gerald DeJean, Darko Kirovski
2007RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
Olivier Savry, Florian Pebay-Peyroula, François Dehmas, Gérard Robert, Jacques Reverdy
2007Secret External Encodings Do Not Prevent Transient Fault Analysis.
Christophe Clavier
2007Side Channel Cryptanalysis of a Higher Order Masking Scheme.
Jean-Sébastien Coron, Emmanuel Prouff, Matthieu Rivain
2007TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Reouven Elbaz, David Champagne, Ruby B. Lee, Lionel Torres, Gilles Sassatelli, Pierre Guillemin
2007Two New Techniques of Side-Channel Cryptanalysis.
Alex Biryukov, Dmitry Khovratovich