CHES A

33 papers

YearTitle / Authors
2005A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis.
Jean-Sébastien Coron, David Lefranc, Guillaume Poupard
2005A Stochastic Model for Differential Side Channel Cryptanalysis.
Werner Schindler, Kerstin Lemke, Christof Paar
2005A Very Compact S-Box for AES.
David Canright
2005AES on FPGA from the Fastest to the Smallest.
Tim Good, Mohammed Benaissa
2005Bipartite Modular Multiplication.
Marcelo E. Kaihara, Naofumi Takagi
2005Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings.
Berk Sunar, David Cyganski
2005Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings
Josyula R. Rao, Berk Sunar
2005DPA Leakage Models for CMOS Logic Circuits.
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
2005Data Remanence in Flash Memory Devices.
Sergei P. Skorobogatov
2005Design of Testable Random Bit Generators.
Marco Bucci, Raimondo Luzzi
2005EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA.
Catherine H. Gebotys, Simon Ho, C. C. Tiu
2005Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.
Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto
2005Energy-Efficient Software Implementation of Long Integer Modular Arithmetic.
Johann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich
2005Fast Truncated Multiplication for Cryptographic Applications.
Laszlo Hars
2005Further Hidden Markov Model Cryptanalysis.
P. J. Green, Richard Noad, Nigel P. Smart
2005Hardware Acceleration of the Tate Pairing in Characteristic Three.
Philipp Grabher, Dan Page
2005Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP.
Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
2005Improved Higher-Order Side-Channel Attacks with FPGA Experiments.
Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
2005Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.
Thomas Popp, Stefan Mangard
2005Masking at Gate Level in the Presence of Glitches.
Wieland Fischer, Berndt M. Gammel
2005On Second-Order Differential Power Analysis.
Marc Joye, Pascal Paillier, Berry Schoenmakers
2005Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
2005Resistance of Randomized Projective Coordinates Against Power Analysis.
William Dupuy, Sébastien Kunz-Jacques
2005SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.
Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke
2005Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization.
Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer
2005Secure Data Management in Trusted Computing.
Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble
2005Security Evaluation Against Electromagnetic Analysis at Design Time.
Huiyun Li, A. Theodore Markettos, Simon W. Moore
2005Security Limits for Compromising Emanations.
Markus G. Kuhn
2005Short Memory Scalar Multiplication on Koblitz Curves.
Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume
2005Successfully Attacking Masked AES Hardware Implementations.
Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald
2005Templates as Master Keys.
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm
2005The "Backend Duplication" Method.
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
2005Using an RSA Accelerator for Modular Inversion.
Martin Seysen