| 2001 | 1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features. Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma |
| 2001 | 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA |
| 2001 | A Decimal Floating-Point Specification. Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Charles F. Webb |
| 2001 | A Design of Radix-2 On-line Division Using LSA Organization. Alexandre F. Tenca, Syed Ubaid Hussaini |
| 2001 | A Family of Adders. Simon Knowles |
| 2001 | A Hardware Algorithm for Computing Reciprocal Square Root. Naofumi Takagi |
| 2001 | Algorithms for Quad-Double Precision Floating Point Arithmetic. Yozo Hida, Xiaoye S. Li, David H. Bailey |
| 2001 | Analysis of Column Compression Multipliers. K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte |
| 2001 | Binary Multiplication Radix-32 and Radix-256. Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
| 2001 | Bounds on Runs of Zeros and Ones for Algebraic Functions. Tomás Lang, Jean-Michel Muller |
| 2001 | Computer Arithmetic-A Processor Architect's Perspective. Ruby B. Lee |
| 2001 | Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. Tomás Lang, Elisardo Antelo |
| 2001 | Effective Continued Fractions. David R. Lester |
| 2001 | Efficient Computation of Multiplicative Inverses for Cryptographic Applications. M. Anwarul Hasan |
| 2001 | Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller |
| 2001 | Generation and Analysis of Hard to Round Cases for Binary Floating Point Division. Lee D. McFearin, David W. Matula |
| 2001 | High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
| 2001 | High-Performance Architectures for Elementary Function Generation. Jun Cao, Belle W. Y. Wei, Jie Cheng |
| 2001 | Improved Table Lookup Algorithms for Postscaled Division. David W. Matula |
| 2001 | In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon-Key Lee, Sang-Woo Kim |
| 2001 | Leading Zero Anticipation and Detection-A Comparison of Methods. Martin S. Schmookler, Kevin J. Nowka |
| 2001 | Low-Power Properties of the Logarithmic Number System. Vassilis Paliouras, Thanos Stouraitis |
| 2001 | Modular Multiplication and Base Extensions in Residue Number Systems. Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
| 2001 | On the Design of Fast IEEE Floating-Point Adders. Peter-Michael Seidel, Guy Even |
| 2001 | On-line Arithmetic for Detection in Digital Communication Receivers. Sridhar Rajagopal, Joseph R. Cavallaro |
| 2001 | Optimised Squaring of Long Integers Using Precomputed Partial Products. Braden Phillips |
| 2001 | Parallel Prefix Adder Design. Andrew Beaumont-Smith, Cheng-Chew Lim |
| 2001 | Some Improvements on Multipartite Table Methods . Florent de Dinechin, Arnaud Tisserand |
| 2001 | The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications. Vassil S. Dimitrov, Jonathan Eskritt, Laurent Imbert, Graham A. Jullien, William C. Miller |
| 2001 | Unrestricted Faithful Rounding is Good Enough for Some LNS Applications. Mark G. Arnold, Colin D. Walter |
| 2001 | Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. Javier D. Bruguera, Tomás Lang |
| 2001 | Worst Cases for Correct Rounding of the Elementary Functions in Double Precision. Vincent Lefèvre, Jean-Michel Muller |