PACT B

69 papers

YearTitle / Authors
20112011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011
Lawrence Rauchwerger, Vivek Sarkar
2011A Compiler-assisted Runtime-prefetching Scheme for Heterogenous Platforms.
Baojiang Shou, Xionghui Hou, Li Chen
2011A Heterogeneous Parallel Framework for Domain-Specific Languages.
Kevin J. Brown, Arvind K. Sujeeth, HyoukJoong Lee, Tiark Rompf, Hassan Chafi, Martin Odersky, Kunle Olukotun
2011A Hierarchical Approach to Maximizing MapReduce Efficiency.
Zhiwei Xiao, Haibo Chen, Binyu Zang
2011A Software-Managed Coherent Memory Architecture for Manycores.
Jung-Ho Park, Choonki Jang, Jaejin Lee
2011A Unified Scheduler for Recursive and Task Dataflow Parallelism.
Hans Vandierendonck, George Tzenakis, Dimitrios S. Nikolopoulos
2011ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment.
Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco
2011An Alternative Memory Access Scheduling in Manycore Accelerators.
Yonggon Kim, Hyunseok Lee, John Kim
2011An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors.
Rance Rodrigues, Israel Koren, Sandip Kundu
2011An Evaluation of Vectorizing Compilers.
Saeed Maleki, Yaoqing Gao, María Jesús Garzarán, Tommy Wong, David A. Padua
2011An OpenCL Framework for Homogeneous Manycores with No Hardware Cache Coherence.
Jun Lee, Jungwon Kim, Junghyun Kim, Sangmin Seo, Jaejin Lee
2011Beforehand Migration on D-NUCA Caches.
Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González
2011Building Retargetable and Efficient Compilers for Multimedia Instruction Sets.
Serge Guelton, Adrien Guinet, Ronan Keryell
2011Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs.
Meng-Ju Wu, Donald Yeung
2011Collaborative Caching for Unknown Cache Sizes.
Xiaoming Gu
2011Compiler Directed Data Locality Optimization for Multicore Architectures.
Wei Ding, Jithendra Srinivas, Mahmut T. Kandemir, Mustafa Karaköy
2011Compiling Dynamic Data Structures in Python to Enable the Use of Multi-core and Many-core Libraries.
Bin Ren, Gagan Agrawal
2011Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU.
Ziyu Guo, Eddy Zheng Zhang, Xipeng Shen
2011CriticalFault: Amplifying Soft Error Effect Using Vulnerability-Driven Injection.
Xin Xu, Man-Lap Li
2011DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism.
Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou
2011Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution.
Neal Clayton Crago, Sanjay J. Patel
2011Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.
Samira Manabi Khan, Daniel A. Jiménez
2011DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal
2011Divergence Analysis and Optimizations.
Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintão Pereira, Wagner Meira Jr.
2011Dynamic Fine-Grain Scheduling of Pipeline Parallelism.
Daniel Sánchez, David Lo, Richard M. Yoo, Jeremy Sugerman, Christos Kozyrakis
2011Efficient Parallel Graph Exploration on Multi-Core CPU and GPU.
Sungpack Hong, Tayo Oguntebi, Kunle Olukotun
2011Enhancing Data Locality for Dynamic Simulations through Asynchronous Data Transformations and Adaptive Control.
Bo Wu, Eddy Z. Zhang, Xipeng Shen
2011Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores.
Junghoon Lee, Minjeong Shin, Hanjoon Kim, John Kim, Jaehyuk Huh
2011Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.
Zhe Wang, Daniel A. Jiménez
2011Exploiting Task Order Information for Optimizing Sequentially Consistent Java Programs.
Christoph Angerer, Thomas R. Gross
2011Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour.
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
2011Improving Run-Time Scheduling for General-Purpose Parallel Code.
Alexandros Tzannes, Rajeev Barua, Uzi Vishkin
2011Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling.
Jungseob Lee, Vijay Sathish, Michael J. Schulte, Katherine Compton, Nam Sung Kim
2011Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy Update.
Anh Vo, Ganesh Gopalakrishnan, Robert M. Kirby, Bronis R. de Supinski, Martin Schulz, Greg Bronevetsky
2011Linear-time Modeling of Program Working Set in Shared Cache.
Xiaoya Xiang, Bin Bao, Chen Ding, Yaoqing Gao
2011MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John
2011MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.
Ping Zhou, Bo Zhao, Youtao Zhang, Jun Yang, Yiran Chen
2011Making STMs Cache Friendly with Compiler Transformations.
Sandya Mannarswamy, Ramaswamy Govindarajan
2011Memory Architecture for Integrating Emerging Memory Technologies.
Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu
2011Modeling and Performance Evaluation of TSO-Preserving Binary Optimization.
Cheng Wang, Youfeng Wu
2011No More Backstabbing... A Faithful Scheduling Policy for Multithreaded Programs.
Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan
2011OpenMDSP: Extending OpenMP to Program Multi-Core DSP.
Jiangzhou He, Wenguang Chen, Guangri Chen, Weimin Zheng, Zhizhong Tang, Handong Ye
2011Optimizing Data Layouts for Parallel Computation on Multicores.
Yuanrui Zhang, Wei Ding, Jun Liu, Mahmut T. Kandemir
2011Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems.
Yi-Hua E. Yang, Viktor K. Prasanna
2011PEPSC: A Power-Efficient Processor for Scientific Computing.
Ganesh S. Dasika, Ankit Sethia, Trevor N. Mudge, Scott A. Mahlke
2011POPS: Coherence Protocol Optimization for Both Private and Shared Data.
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang
2011Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex Applications.
Wenjing Ma, Sriram Krishnamoorthy, Gagan Agrawal
2011Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores.
Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan
2011Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer.
Nikolas Ioannou, Michael Kauschke, Matthias Gries, Marcelo Cintra
2011Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.
Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2011Prediction Based DRAM Row-Buffer Management in the Many-Core Era.
Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis
2011Probabilistic Models Towards Optimal Speculation of DFA Applications.
Zhijia Zhao, Bo Wu
2011Program Interferometry.
Zhe Wang, Daniel A. Jiménez
2011Programming Strategies for GPUs and their Power Consumption.
Sayan Ghosh, Barbara M. Chapman
2011Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.
Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili
2011Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.
Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale
2011SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores.
Sangmin Seo, Junghyun Kim, Jaejin Lee
2011SPATL: Honey, I Shrunk the Coherence Directory.
Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan
2011STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.
Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy.
Yingying Tian, Daniel A. Jiménez
2011Scalable Proximity-Aware Cache Replication in Chip Multiprocessors.
Chongmin Li, Haixia Wang, Yibo Xue, Dongsheng Wang, Jian Li
2011Scalable and Efficient Bounds Checking for Large-Scale CMP Environments.
Baik Song An, Ki Hwan Yum, Eun Jung Kim
2011Speculative Parallelization in Decoupled Look-ahead.
Alok Garg, Raj Parihar, Michael C. Huang
2011StVEC: A Vector Instruction Extension for High Performance Stencil Computation.
Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan
2011SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011TIDeFlow: A Parallel Execution Model for High Performance Computing Programs.
Daniel A. Orozco
2011Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.
Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian
2011Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
2011rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory.
Jie Chen, Zachary Winter, Guru Venkataramani, H. Howie Huang