Zvonko G. Vranesic

80 papers A* 12A 8B 4C 1Misc 2Journal 39Unranked 13
YearRankTypeTitle / Venue / Authors
2013 J jnl
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2009 B conf
Enhancements to FPGA design methodology using streaming.
FPL
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008 — conf
Stream Programming for FPGAs.
FDL (Selected Papers)
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008 C conf
Towards Compilation of Streaming Programs into FPGA Hardware.
FDL
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2007 — conf
On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees.
ICSOFT (PL/DPS/KE/MUSE)
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2006 Misc conf
A Multithreaded Soft Processor for SoPC Area Reduction.
FCCM
Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
2006 B conf
Adaptive FPGAs: High-Level Architecture and a Synthesis Method.
FPL
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006 J jnl
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2005 A conf
Experiences with Soft-Core Processor Design.
IPDPS
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
2003 J jnl
A fast algorithm for OR-AND-OR synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debatosh Debnath, Zvonko G. Vranesic
2003 Misc conf
Use of HDLs in teaching of computer hardware courses.
WCAE
Zvonko G. Vranesic, Stephen Brown
2002 J jnl
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields.
IEEE Trans. Computers
Zeljko Zilic, Zvonko G. Vranesic
2002 B conf
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.
FPL
Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
2001 J jnl
Structural analysis and generation of synthetic digital circuits with memory.
IEEE Trans. Very Large Scale Integr. Syst.
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
2000 B conf
The NUMAchine Multiprocessor.
ICPP
R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1999 J jnl
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.
Int. J. Parallel Program.
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1999 J jnl
The memory/logic interface in FPGAs with large embedded memory arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1998 A* conf
Design and Implementation of the NUMAchine Multiprocessor.
DAC
A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1998 — conf
The FPGA Challenge.
ISMVL
Zvonko G. Vranesic
1998 J jnl
Using Decision Diagrams to Design ULMs for FPGAs.
IEEE Trans. Computers
Zeljko Zilic, Zvonko G. Vranesic
1997 J jnl
Analytical Prediction of Performance for Cache Coherence Protocols.
IEEE Trans. Computers
Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin
1997 A* conf
Memory-System Design Considerations for Dynamically-Scheduled Processors.
ISCA
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1997 A conf
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.
FPGA
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1997 A* conf
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
MICRO
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1996 A* conf
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.
DAC
Stephen Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
1996 J jnl
Minimizing FPGA Interconnect Delays.
IEEE Des. Test Comput.
Stephen Brown, Muhammad M. Khellah, Zvonko G. Vranesic
1996 — conf
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms.
ISMVL
Zeljko Zilic, Zvonko G. Vranesic
1996 A conf
Using BDDs to Design ULMs for FPGAs.
FPGA
Zeljko Zilic, Zvonko G. Vranesic
1995 J jnl
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions.
IEEE Trans. Computers
Zeljko Zilic, Zvonko G. Vranesic
1995 A conf
Architecture of Centralized Field-Configurable Memory.
FPGA
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1995 — conf
Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings.
Euro-Par
Muhammad Jaseemuddin, Zvonko G. Vranesic
1995 — conf
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation.
ISMVL
Zeljko Zilic, Zvonko G. Vranesic
1995 J jnl
Scalable cache consistency for hierarchically structured multiprocessors.
J. Supercomput.
Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm
1994 — conf
On Scheduling in Multiprocessor Systems Using Fuzzy Logic.
ISMVL
Alireza Kaviani, Zvonko G. Vranesic
1994 A conf
Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems.
HPDC
Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin
1993 J jnl
A stochastic model to predict the routability of field-programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
1993 — conf
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor.
SPDP
Steven J. E. Wilton, Zvonko G. Vranesic
1993 — conf
Current-Mode CMOS Galois Field Circuits.
ISMVL
Zeljko Zilic, Zvonko G. Vranesic
1993 J jnl
Physically Based Modeling and Control of Turning.
CVGIP Graph. Model. Image Process.
Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
1992 J jnl
A detailed router for field-programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Stephen Brown, Jonathan Rose, Zvonko G. Vranesic
1992 A conf
Cache Consistency in Hierarchical-Ring-Based Multiprocessors.
SC
Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm
1992 — conf
Towards the Realization of 4-Valued CMOS Circuits.
ISMVL
Konrad Lei, Zvonko G. Vranesic
1991 A* conf
A Hybrid Token/Insertion Ring LAN.
INFOCOM
Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky
1991 J jnl
Algorithmic Synthesis of MVL Functions for CCD Implementation.
IEEE Trans. Computers
Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky
1991 A* conf
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs.
DAC
Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
1991 J jnl
Hector: A Hierarchically Structured Shared-memory Multiprocessor.
Computer
Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White
1991 — conf
On the Synthesis of 4-Valued Current Mode CMOS Circuits.
ISMVL
Konrad Lei, Zvonko G. Vranesic
1991 A* ed.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991
ISCA
Zvonko G. Vranesic
1991 A conf
Technology Mapping on Lookup Table-Based FPGAs for Performance.
ICCAD
Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
1990 A conf
A Detailed Router for Field-Programmable Gate Arrays.
ICCAD
Stephen Brown, Jonathan Rose, Zvonko G. Vranesic
1990 — book
Computer organization, 3rd Edition.
V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky
1990 J jnl
Cost Reduction in the CCD Realization of MVMT Function.
IEEE Trans. Computers
Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic
1990 A* conf
Reusable motion synthesis using state-space controllers.
SIGGRAPH
Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
1990 — conf
Step-Wise Synthesis of CCD MVL Functions.
ISMVL
Safwat G. Zaky, Zvonko G. Vranesic, Mostafa I. H. Abd-El-Barr
1990 A* conf
TORMLAN - A Multichannel Local Area Network Protocol.
INFOCOM
Lap-kong Chan, Zvonko G. Vranesic
1989 J jnl
Using active components to perform voltage division in digital-to-analog conversion.
IEEE J. Solid State Circuits
Chu Phoon Chong, Kenneth C. Smith, Zvonko G. Vranesic
1988 J jnl
Parallel standard cell placement algorithms with quality equivalent to simulated annealing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic
1986 J jnl
Implementation of a Dynamic Address Assignment Protocol in a Local Area Network.
Comput. Networks
Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic
1986 J jnl
Synthesis of Multivalued Multithreshold Functions for CCD Implementation.
IEEE Trans. Computers
Mostafa I. H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic
1985 J jnl
FERMTOR: A Tunable Multiprocessor Architecture.
IEEE Micro
Jonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic
1984 J jnl
Comments on "Fault Diagnosis of MOS Combinational Networks".
IEEE Trans. Computers
Kuang-Wei Chiang, Zvonko G. Vranesic
1983 J jnl
A Pipelined Distributed Arithmetic PFFT Processor.
IEEE Trans. Computers
Paul Chow, Zvonko G. Vranesic, Jui Lin Yen
1983 J jnl
A Tree Representation of Combinational Networks.
IEEE Trans. Computers
Kuang-Wei Chiang, Zvonko G. Vranesic
1983 A* conf
On fault detection in CMOS logic networks.
DAC
Kuang-Wei Chiang, Zvonko G. Vranesic
1981 J jnl
Key compression using segment strings.
Inf. Syst.
C. L. Lam, Zvonko G. Vranesic
1981 A* conf
TORNET: A local area network.
SIGCOMM
Zvonko G. Vranesic, V. Carl Hamacher, Wayne M. Loucks, Safwat G. Zaky
1980 J jnl
Teaching Computer Structures.
Computer
Zvonko G. Vranesic, Kenneth J. Thurber, Sperry Univac
1980 J jnl
Ternary Rate-Multipliers.
IEEE Trans. Computers
Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic
1978 J jnl
A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks.
IEEE Trans. Computers
A. Druzeta, Zvonko G. Vranesic
1978 J jnl
Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976.
SIGARCH Comput. Archit. News
Zvonko G. Vranesic
1977 — conf
Experiences with CHUTE.
ACM Annual Conference
F. M. Valenti, Zvonko G. Vranesic
1977 J jnl
Multiple-Valued Logic: An Introduction and Overview.
IEEE Trans. Computers
Zvonko G. Vranesic
1974 J jnl
Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks.
IEEE Trans. Computers
A. Druzeta, Zvonko G. Vranesic, A. S. Sedra
1974 J jnl
Engineering aspects of multi-valued logic systems.
Computer
Zvonko G. Vranesic, Kenneth C. Smith
1974 J jnl
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines.
IEEE Trans. Computers
Donald A. Sheppard, Zvonko G. Vranesic
1973 A* conf
Design of a Fully Variable - Length Structured Minicomputer.
ISCA
Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung
1972 J jnl
Functional Transformation in Simplification of Multivalued Switching Functions.
IEEE Trans. Computers
Zvonko G. Vranesic, K. M. Waliuzzaman
1972 J jnl
Ternary logic in parallel multipliers.
Comput. J.
Zvonko G. Vranesic, V. Carl Hamacher
1970 J jnl
A Many-Valued Algebra for Switching Systems.
IEEE Trans. Computers
Zvonko G. Vranesic, E. Stewart Lee, Kenneth C. Smith
1970 J jnl
On Decomposition of Multi-Valued Switching Functions.
Comput. J.
K. M. Waliuzzaman, Zvonko G. Vranesic