Zuocheng Xing - RankMe

61 papers A* 1B 1C 3Misc 1Journal 25Unranked 30

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map. Sensors Zerun Li, Qinglin Wang, Yufei Zhu, Zuocheng Xing
2021	—	`conf`	A Noc Centric Low Overhead Multi-chip Interconnection Technology. HPCC/DSS/SmartCity/DependSys Xing Hu, Yang Zhang, Li Mao, Jie Shen, Zuocheng Xing
2021	J	`jnl`	Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph. IEEE Access Yufei Zhu, Zuocheng Xing, Jinhui Xue, Zerun Li, Yifan Hu, Yang Zhang, Yongzhong Li
2021	J	`jnl`	High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes. Symmetry Yufei Zhu, Zuocheng Xing, Zerun Li, Yang Zhang, Yifan Hu
2021	J	`jnl`	Low latency group-sorted QR decomposition algorithm for larger-scale MIMO systems. IET Commun. Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yongzhong Li
2020	Misc	`conf`	A Low-Latency Successive Cancellation Hybrid Decoder for Convolutional Polar Codes. ICASSP Yu Wang, Shikai Qiu, Lirui Chen, Qinglin Wang, Yang Zhang, Cang Liu, Zuocheng Xing
2020	C	`conf`	A Paralleled Greedy LLL Algorithm for 16×16 MIMO Detection. ISCAS Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yang Zhang
2020	J	`jnl`	An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture. IEEE Access Yu Wang, Qinglin Wang, Yang Zhang, Shikai Qiu, Zuocheng Xing
2020	J	`jnl`	Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm. IEEE Access Lirui Chen, Zuocheng Xing, Yongzhong Li, Shikai Qiu
2020	J	`jnl`	Practical AMC model based on SAE with various optimisation methods under different noise environments. IET Commun. Zerun Li, Qinglin Wang, Weisong Liu, Qiang Xu, Zuocheng Xing, Yongzhong Li
2019	B	`conf`	Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes. WCNC Yu Wang, Lirui Chen, Qinglin Wang, Yang Zhang, Zuocheng Xing
2019	J	`jnl`	An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture. IEEE Access Yu Wang, Lirui Chen, Cang Liu, Zuocheng Xing
2019	—	`conf`	Optimization Methods for Computing System in Mobile CPS. ICBDT Yang Zhang, Zuocheng Xing, Yu Wang, Lirui Chen, Qinglin Wang, Yufei Zhu
2018	—	`conf`	A Low Latency SCAN-Flip Polar Decoder for 5G Vehicular Communication. INTSYS Yu Wang, Lirui Chen, Shikai Qiu, Li Huang, Zuocheng Xing
2018	J	`jnl`	CWLP: coordinated warp scheduling and locality-protected cache allocation on GPUs. Frontiers Inf. Technol. Electron. Eng. Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang
2018	J	`jnl`	Locality based warp scheduling in GPGPUs. Future Gener. Comput. Syst. Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Qinglin Wang
2018	J	`jnl`	Locality-protected cache allocation scheme with low overhead on GPUs. IET Comput. Digit. Tech. Yang Zhang, Zuocheng Xing, Chuan Tang, Cang Liu
2017	J	`jnl`	A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation. IEEE Trans. Very Large Scale Integr. Syst. Luechao Yuan, Cang Liu, Chuan Tang, Shan Huang, Anupam Chattopadhyay, Gerd Ascheid, Zuocheng Xing
2017	J	`jnl`	A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs Cang Liu, Zuocheng Xing, Luechao Yuan, Chuan Tang, Yang Zhang
2017	J	`jnl`	Approximate iteration detection with iterative refinement in massive MIMO systems. IET Commun. Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
2017	J	`jnl`	Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yang Zhang
2017	J	`jnl`	Low latency QRD algorithm for future communication. IEICE Electron. Express Lirui Chen, Cang Liu, Yu Wang, Zuocheng Xing, Yang Zhang, Jing Liu
2016	—	`conf`	An Architecture of Parallel Tiled QRD Algorithm for MIMO-OFDM Systems. Trustcom/BigDataSE/ISPA Cang Liu, Chuan Tang, Zuocheng Xing, Lirui Chen, Yang Zhang, Guitao Fu
2016	—	`conf`	Hardware design of ML algorithm in MIMO-OFDM system. ICSAI Suncheng Xiang, Minxuan Zhang, Zuocheng Xing, Cang Liu
2016	J	`jnl`	High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO. IEEE Commun. Lett. Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
2016	—	`conf`	Locality Protected Dynamic Cache Allocation Scheme on GPUs. Trustcom/BigDataSE/ISPA Yang Zhang, Zuocheng Xing, Li Zhou, Chunsheng Zhu
2016	—	`conf`	Optimization of Two Bottleneck Programs in SAR System on GPGPU. NCCET Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Lirui Chen, Qinglin Wang
2016	J	`jnl`	QR decomposition architecture using the iteration look-ahead modified Gram-Schmidt algorithm. IET Circuits Devices Syst. Cang Liu, Chuan Tang, Luechao Yuan, Zuocheng Xing, Yang Zhang
2016	—	`conf`	QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems. WICON Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yu Wang, Lirui Chen, Yang Zhang, Suncheng Xiang, Wangfeng Zhao, Xing Hu, Jinsong Xu
2015	—	`conf`	A GPU-based Fast Solution for Riesz Space Fractional Reaction-Diffusion Equation. NBiS Qinglin Wang, Jie Liu, Chunye Gong, Yang Zhang, Zuocheng Xing
2015	—	`conf`	A ML-Based High-Accuracy Estimation of Sampling and Carrier Frequency Offsets for OFDM Systems. NCCET Cang Liu, Luechao Yuan, Zuocheng Xing, Xiantuo Tang, Guitao Fu
2015	C	`conf`	A flexible low-complexity robust THP approach for MISO downlinks with imperfect CSI. ICCC Luechao Yuan, Gaojiang Wang, Gerd Ascheid, Cang Liu, Zuocheng Xing
2015	—	`conf`	Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. PACRIM Qinglin Wang, Jie Liu, Xiantao Cui, Guitao Fu, Chunye Gong, Zuocheng Xing
2015	J	`jnl`	Applying Partial Power-Gating to Direction-Sliced Network-on-Chip. J. Electr. Comput. Eng. Feng Wang, Xiantuo Tang, Zuocheng Xing
2015	J	`jnl`	Applying partial power-gating to bit-sliced network-on-chip. Microelectron. J. Feng Wang, Xiantuo Tang, Zuocheng Xing
2015	—	`conf`	Channel Estimation in Massive MIMO: Algorithm and Hardware. NCCET Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
2015	—	`conf`	DIPP - An LLC Replacement Policy for On-chip Dynamic Heterogeneous Multi-core Architecture. ICYCSEE Yang Zhang, Zuocheng Xing, Xiao Ma
2015	—	`conf`	Memory Access Analysis of Many-core System with Abundant Bandwidth. MCSoC Chuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu
2015	—	`conf`	UniMESH: The light-weight unidirectional channel Network-on-Chip in 2D mesh topology. CONIELECOMP Feng Wang, Xiantuo Tang, Zuocheng Xing, Hengzhu Liu
2014	C	`conf`	Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip. DSD Feng Wang, Xiantuo Tang, Qinglin Wang, Zuocheng Xing, Hengzhu Liu
2014	—	`conf`	Parallel 3D deterministic particle transport on Intel MIC architecture. HPCS Qinglin Wang, Zuocheng Xing, Jie Liu, Xiaogang Qiang, Chunye Gong, Jiang Jiang
2014	—	`conf`	The acceleration of turbo decoder on the newest GPGPU of Kepler architecture. ISCIT Yang Zhang, Zuocheng Xing, Luechao Yuan, Cang Liu, Qinglin Wang
2013	—	`conf`	A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. NCCET Xiaobao Chen, Zuocheng Xing, Bingcai Sui
2013	J	`jnl`	Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing
2013	—	`conf`	An Optimizing Strategy Research of LDPC Decoding Based on GPGPU. TrustCom/ISPA/IUCC Luechao Yuan, Zuocheng Xing, Yang Zhang, Xiaobao Chen
2013	J	`jnl`	Architecture and Implementation of a Reduced EPIC Processor. IEICE Trans. Inf. Syst. Jun Gao, Minxuan Zhang, Zuocheng Xing, Chaochao Feng
2013	—	`conf`	Backhaul-Route Pre-Configuration Mechanism for Delay Optimization in NoCs. NCCET Xiantuo Tang, Feng Wang, Zuocheng Xing, Qinglin Wang
2013	J	`jnl`	Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors. IEICE Electron. Express Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shi-Ce Ni
2013	—	`conf`	Tunable Negative Differential Resistance of Single-Electron Transistor Controlled by Capacitance. NCCET Xiaobao Chen, Zuocheng Xing, Bingcai Sui
2012	—	`conf`	Validation and analysis of negative differential resistance of single-electron transistor with conductance model. ICECS Xiaobao Chen, Zuocheng Xing, Bingcai Sui
2011	—	`conf`	A model for energy quantization of single-electron transistor below 10nm. ASICON Xiaobao Chen, Zuocheng Xing, Bingcai Sui
2011	J	`jnl`	Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design. J. Comput. Sci. Technol. Anguo Ma, Yu Cheng, Zuocheng Xing
2011	—	`conf`	Characterizing Time-Varying Behavior and Predictability of Cache AVF. INCoS Yu Cheng, Yongwen Wang, Zuocheng Xing, Minxuan Zhang
2011	—	`conf`	Design and Evaluation of Traffic Filter for Token Protocol. PARELEC Guitao Fu, Zuocheng Xing, Tianlei Zhao, Xiantuo Tang
2010	—	`conf`	A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. ISVLSI Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang
2009	—	`conf`	Design of Testing Struture in Microprocessor Based on JTAG. ISCID (1) Ping Zhang, Yanmin Song, Jianmin Zhang, Zuocheng Xing
2009	J	`jnl`	Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. IEEE Trans. Parallel Distributed Syst. Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang
2009	—	`conf`	Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing
2009	—	`conf`	Performance Optimization Strategies of High Performance Computing on GPU. APPT Anguo Ma, Jing Cai, Yu Cheng, Xiaoqiang Ni, Yuxing Tang, Zuocheng Xing
2007	A*	`conf`	A 64-bit stream processor architecture for scientific applications. ISCA Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang
2006	—	`conf`	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing