Zunsong Yang

19 papers Journal 8Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
25.10 A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks.
ISSCC
Kai Cheng, Yunbo Huang, Zunsong Yang, Li Wang, Hongyu Ren, Xiaoyu Shan, Pui-In Mak, Yong Chen, Bo Li
2025 — conf
A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2
CICC
Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui Paulo Martins, Yan Lu, Nan Sun, Nan Qi, Yong Chen
2025 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment.
IEEE J. Solid State Circuits
Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
2025 J jnl
An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC.
Circuits Syst. Signal Process.
Shuowei Li, Zunsong Yang, Tetsuya Iizuka
2025 — conf
Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection.
ASP-DAC
Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2024 — conf
7.4 A 0.027mm
ISSCC
Yunbo Huang, Yong Chen, Zunsong Yang, Rui Paulo Martins, Pui-In Mak
2024 — conf
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.
VLSI Technology and Circuits
Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
2024 J jnl
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering.
IEEE J. Solid State Circuits
Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
2024 J jnl
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
2023 — conf
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit.
ICICDT
Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2023 — conf
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.
VLSI Technology and Circuits
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
2023 — conf
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit.
ICICDT
Zhenyu Cheng, Zunsong Yang, Yuyang Zhu, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2022 — conf
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
VLSI Technology and Circuits
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
2022 J jnl
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.
IEEE Trans. Very Large Scale Integr. Syst.
Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, Rui Paulo Martins
2021 J jnl
A 0.003-mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2020 J jnl
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
2019 — conf
A 0.003-mm
A-SSCC
Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.0071-mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins
2019 — conf
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
ISSCC
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins