Zule Xu - RankMe

32 papers C 2Journal 17Unranked 13

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End. ISSCC Anoop Narayan Bhat, Paul Mateman, Zule Xu, Peter Vis, Paul Detterer, Gururaja Kasanadi Ramachandra, Yunus Baykal, Mario Konijnenburg, Yao-Hong Liu, Christian Bachmann, Peng Zhang
2024	J	`jnl`	A 7.6-mW IR-UWB Receiver Achieving -17-dBm Blocker Resilience With a Linear RF Front-End. IEEE J. Solid State Circuits Anoop Narayan Bhat, Paul Mateman, Zule Xu, Peter Vis, Paul Detterer, Gururaja Kasanadi Ramachandra, Yunus Baykal, Mario Konijnenburg, Yao-Hong Liu, Christian Bachmann, Peng Zhang
2024	J	`jnl`	A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
2023	J	`jnl`	A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. IEICE Trans. Electron. Masaya Miyahara, Zule Xu, Takehito Ishii, Noritoshi Kimura
2022	—	`conf`	A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
2022	C	`conf`	A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
2022	J	`jnl`	A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration. IEEE J. Solid State Circuits Zule Xu
2022	—	`conf`	An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC Masaru Osada, Zule Xu, Tetsuya Iizuka
2022	J	`jnl`	Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
2021	—	`conf`	A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref. A-SSCC Zule Xu
2021	—	`conf`	A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits Zule Xu, Masaru Osada, Tetsuya Iizuka
2021	J	`jnl`	An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka
2020	—	`conf`	A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits Masaru Osada, Zule Xu, Tetsuya Iizuka
2019	—	`conf`	A 0.0053-mm NEWCAS Naoki Ojima, Zule Xu, Tetsuya Iizuka
2019	J	`jnl`	A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
2019	—	`conf`	An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. IEICE Trans. Electron. Zule Xu, Takayuki Kawahara
2017	J	`jnl`	High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2017	J	`jnl`	Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. IEICE Trans. Electron. Mitsutoshi Sugawara, Zule Xu, Akira Matsuzawa
2017	J	`jnl`	Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. IEICE Trans. Electron. Yasushi Fukuda, Zule Xu, Takayuki Kawahara
2016	—	`conf`	A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	C	`conf`	A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC Zule Xu, Masaya Miyahara, Akira Matsuzawa
2015	J	`jnl`	Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2014	—	`conf`	A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. CICC Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. NEWCAS Zule Xu, Masaya Miyahara, Akira Matsuzawa
2012	J	`jnl`	Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Gyu Lee, Zule Xu, Shoichi Masui
2011	J	`jnl`	Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL. IEICE Trans. Electron. Zule Xu, Jun Gyu Lee, Shoichi Masui