Zsolt Tokei - RankMe

23 papers A 4C 1Journal 6Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines. IEEE Trans. Very Large Scale Integr. Syst. Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Prashant Dubey, Chenyun Pan
2025	—	`conf`	Leakage and TDDB Mechanisms in 18 nm Pitch Direct Metal Etch Ru Interconnects with Airgaps. IRPS Alicja Lesniewska, Y. Fang, G. Delie, Philippe Roussel, Koen Van Sever, Emmanuel Chery, O. Varela Pedreira, Ivan Ciofi, S. H. Park, Zsolt Tokei, Kris Croes
2025	J	`jnl`	System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes. ACM Trans. Embed. Comput. Syst. Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2024	J	`jnl`	Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes. IEEE Embed. Syst. Lett. Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2024	—	`conf`	Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. VLSI Technology and Circuits Anshul Gupta, Shreya Kundu, Stefan Decoster, K. Sah, G. Delie, B. Truijen, Davide Tierno, Giulio Marti, O. Varela Pedreira, B. Kenens, Y. Hermans, C. Adelmann, B. de Wachter, Ivan Ciofi, G. Murdoch, A. Cross, Seongho Park, Zsolt Tokei
2024	J	`jnl`	Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. IEEE Trans. Circuits Syst. I Regul. Pap. Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Dawit Burusie Abdi, James Myers, Chenyun Pan
2023	A	`conf`	Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes. DATE Mahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2023	—	`conf`	Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. ISQED Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2023	—	`conf`	Integration of a Stacked Contact MOL for Monolithic CFET. VLSI Technology and Circuits Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei
2023	—	`conf`	Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. ACM Great Lakes Symposium on VLSI Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2023	—	`conf`	Towards accurate temperature prediction in BEOL for reliability assessment (Invited). IRPS Melina Lofrano, Herman Oprins, Xinyue Chang, Bjorn Vermeersch, Olalla Varela Pedreira, Alicja Lesniewska, Vladimir Cherman, Ivan Ciofi, Kristof Croes, Seongho Park, Zsolt Tokei
2022	—	`conf`	First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. VLSI Technology and Circuits Gayle Murdoch, Matin O'Toole, Giulio Marti, Ankit Pokhrel, Diana Tsvetanova, Stefan Decoster, Shreya Kundu, Yusuke Oniki, Arame Thiam, Quoc Toan Le, Olalla Varela Pedreira, Alicja Lesniewska, Gerardo Martinez-Alanis, Seongho Park, Zsolt Tokei
2022	A	`conf`	Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene. FPGA Zsolt Tokei
2021	—	`conf`	Electromigration limits of copper nano-interconnects. IRPS Houman Zahedmanesh, Olalla Varela Pedreira, Zsolt Tokei, Kristof Croes
2021	A	`conf`	Global Is the New Local: FPGA Architecture at 5nm and Beyond. FPGA Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne
2017	J	`jnl`	Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
2015	—	`conf`	Holisitic device exploration for 7nm node. CICC Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen
2015	A	`conf`	Impact of interconnect multiple-patterning variability on SRAMs. DATE Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene
2015	—	`conf`	Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. ISQED Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi
2014	J	`jnl`	Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. Microelectron. Reliab. Bart Vandevelde, Andrej Ivankovic, B. Debecker, Melina Lofrano, Kris Vanstreels, Wei Guo, Vladimir Cherman, Marcel Gonzalez, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Zsolt Tokei
2014	—	`conf`	Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
2008	—	`conf`	A tool flow for predicting system level timing failures due to interconnect reliability degradation. ACM Great Lakes Symposium on VLSI Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor
2006	C	`conf`	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. VLSI-SoC Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei