Ziyi Wang

22 papers A* 4A 3Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2026 — conf
DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks.
ASP-DAC
Rongliang Fu, Libo Shen, Ziyi Wang, Zhengxing Lei, Zixiao Wang, JunYing Huang, Bei Yu, Tsung-Yi Ho
2026 J jnl
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst.
Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 J jnl
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, Bei Yu
2025 — conf
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays.
ISPD
Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, Bei Yu
2025 — conf
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
ISPD
Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025 A conf
NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times.
ICCAD
Ziyi Wang, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, Bei Yu
2025 A conf
PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning.
ICCAD
Seunggeun Kim, Ziyi Wang, Sungyoung Lee, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan
2025 J jnl
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2025 J jnl
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu
2025 J jnl
Prerouting Timing Prediction Across Different Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Jiaxi Jiang, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu
2025 J jnl
Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits.
CoRR
Sungyoung Lee, Ziyi Wang, Seunggeun Kim, Taekyun Lee, David Z. Pan
2025 J jnl
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2024 A* conf
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes.
DAC
Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 — conf
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ISPD
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2023 A* conf
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.
DAC
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu
2023 A* conf
Restructure-Tolerant Timing Prediction via Multimodal Fusion.
DAC
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2022 A* conf
Functionality matters in netlist representation learning.
DAC
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang
2021 A conf
Graph Learning-Based Arithmetic Block Identification.
ICCAD
Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu