Ziyad Hanna

32 papers A* 4A 7B 4Misc 1Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2015 B conf
Democratization of Formal Verification with Collective Intelligence.
FMCAD
Ziyad Hanna
2014 B conf
Challenging problems in industrial formal verification.
FMCAD
Ziyad Hanna
2012 — conf
Formal Analysis of Security Data Paths in RTL Design.
Haifa Verification Conference
Jamil Mazzawi, Ziyad Hanna
2011 — —
A symbolic execution framework for algorithm-level modelling and verification of computer microarchitecture.
Ziyad Hanna
2009 — conf
A symbolic execution framework for algorithm-level modelling.
HLDVT
Ziyad Hanna, Thomas F. Melham
2007 A* conf
A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems.
CAV
Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani
2007 Misc conf
Abstract Modeling and Formal Verification of Microprocessors.
CSR
Ziyad Hanna
2007 — conf
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.
ATS
Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna
2007 B conf
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.
FMCAD
Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili
2007 J jnl
Space-Efficient Bounded Model Checking
CoRR
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
2007 A conf
Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.
SAT
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
2006 J jnl
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction
CoRR
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
2006 A conf
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction.
SAT
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
2006 — conf
Generation of shorter sequences for high resolution error diagnosis using sequential SAT.
ASP-DAC
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
2006 B conf
Post-reboot Equivalence and Compositional Verification of Hardware.
FMCAD
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
2005 A conf
A Clause-Based Heuristic for SAT Solvers.
SAT
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
2005 A conf
Bounded Model Checking with QBF.
SAT
Nachum Dershowitz, Ziyad Hanna, Jacob Katz
2005 — conf
Encoding RTL Constructs for MathSAT: a Preliminary Report.
PDPAR@CAV
Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani
2005 — conf
Simultaneous SAT-Based Model Checking of Safety Properties.
Haifa Verification Conference
Zurab Khasidashvili, Alexander Nadel, Amit Palti, Ziyad Hanna
2005 A conf
Space-Efficient Bounded Model Checking.
DATE
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
2004 J jnl
A Signal Correlation Guided Circuit-SAT Solver.
J. Univers. Comput. Sci.
Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
2004 — conf
Parallel Multithreaded Satisfiability Solver: Design and Implementation.
PDMC
Yulik Feldman, Nachum Dershowitz, Ziyad Hanna
2004 A conf
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.
ICCAD
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
2003 A* conf
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
DAC
Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
2003 J jnl
Design automation with mixtures of proof strategies for propositional logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
2003 — conf
SAT-based methods for sequential hardware equivalence verification without synchronization.
BMC@CAV
Zurab Khasidashvili, Ziyad Hanna
2002 A* conf
A proof engine approach to solving combinational design automation problems.
DAC
Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
2002 — conf
Alignability equivalence of synchronous sequential circuits.
HLDVT
Amnon Rosenmann, Ziyad Hanna
2002 A conf
High capacity and automatic functional extraction tool for industrial VLSI circuit designs.
ICCAD
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
2002 — conf
TRANS: efficient sequential verification of loop-free circuits.
HLDVT
Zurab Khasidashvili, John Moondanos, Ziyad Hanna
2001 — conf
An enhanced cut-points algorithm in formal equivalence verification.
HLDVT
Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna
2001 A* conf
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV
John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss