Ziran Zhu

50 papers A* 12A 5B 1Misc 1Journal 26Unranked 5
YearRankTypeTitle / Venue / Authors
2026 — conf
A Timing-Driven Hierarchical Macro Placement Framework for Large-Scale Complex IP Blocks.
ASP-DAC
Wei Fu, Lixin Chen, Jinghui Zhou, Ziran Zhu
2026 — conf
Comprehensive Delay-Aware Net Weighting Framework for Timing-Driven Global Placement.
ASP-DAC
Lixin Chen, Keyu Peng, Jinghui Zhou, Hao Gu, Wei Fu, Shuting Cai, Ziran Zhu
2026 — conf
GPU-Accelerated Global Routing with Balanced Timing and Congestion Optimization.
ASP-DAC
Jinghui Zhou, Fuxing Huang, Lixin Chen, Xinglin Zheng, Ziran Zhu
2025 A* conf
Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells.
DAC
Zhengzhe Zheng, Yinuo Wu, Keyu Peng, Chao Wang, Ziran Zhu
2025 A conf
DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO.
ICCAD
Keyu Peng, Yinuo Wu, Zhengzhe Zheng, Hao Gu, Ziran Zhu, Chao Wang, Jun Yang
2025 J jnl
Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu, Jianli Chen, Jun Yang
2025 J jnl
Fast Training-free Perceptual Image Compression.
CoRR
Ziran Zhu, Tongda Xu, Minye Huang, Dailan He, Xingtong Ge, Xinjie Zhang, Ling Li, Yan Wang
2025 A* conf
Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning.
DAC
Xinglin Zheng, Hao Gu, Keyu Peng, Youwen Wang, Wenxing Zhu, Ziran Zhu
2025 A conf
Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement.
DATE
Hao Gu, Xinglin Zheng, Youwen Wang, Keyu Peng, Ziran Zhu, Jun Yang
2025 J jnl
NaViL: Rethinking Scaling Properties of Native Multimodal Large Language Models under Data Constraints.
CoRR
Changyao Tian, Hao Li, Gen Luo, Xizhou Zhu, Weijie Su, Hanming Deng, Jinguo Zhu, Jie Shao, Ziran Zhu, Yunpeng Liu, Lewei Lu, Wenhai Wang, Hongsheng Li, Jifeng Dai
2025 J jnl
Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Gu, Jian Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu
2025 J jnl
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB.
Integr.
Disi Lin, Chuandong Chen, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin, Jianli Chen
2024 J jnl
A fast and high-performance global router with enhanced congestion control.
Integr.
Xiqiong Bai, Yilu Chen, Zhifeng Lin, Min Wei, Zhijie Cai, Ziran Zhu, Jianli Chen
2024 J jnl
An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting.
IEEE Trans. Circuits Syst. II Express Briefs
Ziran Zhu, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang
2024 J jnl
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs.
Integr.
Zijun Li, Ziran Zhu, Huan He, Jianli Chen
2024 J jnl
Consistency Models Improve Diffusion Inverse Solvers.
CoRR
Tongda Xu, Ziran Zhu, Dailan He, Yuanyuan Wang, Ming Sun, Ning Li, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang
2024 J jnl
High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning.
IEEE Trans. Circuits Syst. II Express Briefs
Ziran Zhu, Yuejian Shi, Yangjie Mei, Fuheng Shen, Hong Liu, Jun Yang
2024 J jnl
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang
2024 A* conf
Idempotence and Perceptual Image Compression.
ICLR
Tongda Xu, Ziran Zhu, Dailan He, Yanghao Li, Lina Guo, Yuanyuan Wang, Zhe Wang, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang
2024 J jnl
Idempotence and Perceptual Image Compression.
CoRR
Tongda Xu, Ziran Zhu, Dailan He, Yanghao Li, Lina Guo, Yuanyuan Wang, Zhe Wang, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang
2024 J jnl
LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks.
IEEE Trans. Circuits Syst. II Express Briefs
Hao Gu, Jian Gu, Keyu Peng, Ziran Zhu, Ning Xu, Xin Geng, Jun Yang
2024 A* conf
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints.
DAC
Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu
2024 A conf
Noise Dimension of GAN: An Image Compression Perspective.
ICME
Ziran Zhu, Tongda Xu, Ling Li, Yan Wang
2024 J jnl
Noise Dimension of GAN: An Image Compression Perspective.
CoRR
Ziran Zhu, Tongda Xu, Ling Li, Yan Wang
2024 J jnl
Subgraph matching-based reference placement for printed circuit board designs.
J. Supercomput.
Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang
2024 B conf
Variational Label-Correlation Enhancement for Congestion Prediction.
ASPDAC
Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang
2023 Misc conf
A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning.
ICMLC
Ke Liu, Jian Gu, Hao Gu, Ziran Zhu
2023 A* conf
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints.
DAC
Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang
2023 — conf
Efficient Global Optimization for Large Scaled Ordered Escape Routing.
ASP-DAC
Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen
2023 J jnl
Variational Label-Correlation Enhancement for Congestion Prediction.
CoRR
Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang
2022 A conf
A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints.
ICCAD
Ziran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, Jun Yang
2022 A* conf
High-performance placement for large-scale heterogeneous FPGAs with clock constraints.
DAC
Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang
2022 J jnl
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang
2022 J jnl
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang
2022 A* conf
Subgraph matching based reference placement for PCB designs: late breaking results.
DAC
Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang
2022 J jnl
Timing-Aware Fill Insertions With Design-Rule and Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang
2022 — conf
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
ASP-DAC
Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang
2021 J jnl
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization.
ACM Trans. Design Autom. Electr. Syst.
Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang
2021 A* conf
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints.
DAC
Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen
2021 A* conf
Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
DAC
Xiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen
2021 J jnl
Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles.
Complex.
Ziran Zhu, Zhipeng Huang, Jianli Chen, Longkun Guo
2020 J jnl
An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.
IEEE Access
Zhipeng Huang, Zhifeng Lin, Ziran Zhu, Jianli Chen
2020 A* conf
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation.
DAC
Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang
2020 J jnl
Mixed-Cell-Height Legalization Considering Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang
2020 J jnl
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect.
Integr.
Ziran Zhu, Zhipeng Huang, Peng Yang, Wenxing Zhu, Jianli Chen, Hanbin Zhou, Senhua Dong
2018 A* conf
Generalized augmented lagrangian and its applications to VLSI global placement.
DAC
Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang
2018 A conf
Mixed-cell-height legalization considering technology and region constraints.
ICCAD
Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang
2017 J jnl
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning.
Integr.
Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu
2017 J jnl
Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition.
IEEE Trans. Computers
Xingquan Li, Ziran Zhu, Wenxing Zhu
2017 A* conf
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs.
DAC
Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang