Zihao Xuan

16 papers A* 2B 1C 1Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design.
CoRR
Wei Xuan, Zihao Xuan, Rongliang Fu, Ning Lin, Kwunhang Wong, Zikang Yuan, Lang Feng, Zhongrui Wang, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025 J jnl
A dynamic decoder with speculative termination for low latency inference in spiking neural networks.
Neurocomputing
Yuxuan Yang, Zihao Xuan, Song Chen, Yi Kang
2025 J jnl
A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks.
Integr.
Yuxuan Yang, Qihu Xie, Zihao Xuan, Song Chen, Yi Kang
2025 J jnl
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity.
ACM Trans. Design Autom. Electr. Syst.
Yuang Ma, Yulong Meng, Zihao Xuan, Song Chen, Yi Kang
2025 J jnl
Informed Routing in LLMs: Smarter Token-Level Computation for Faster Inference.
CoRR
Chao Han, Yijuan Liang, Zihao Xuan, Daokuan Wu, Wei Zhang, Xiaoyu Shen
2025 A* conf
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy.
DAC
Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025 J jnl
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy.
CoRR
Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025 A* conf
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI.
DAC
Zihao Xuan, Yuxuan Yang, Wei Xuan, Zijia Su, Song Chen, Yi Kang
2024 B conf
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron.
ASPDAC
Yuxuan Yang, Zihao Xuan, Yi Kang
2023 — conf
A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing.
ASICON
Yuchao Zhang, Zihao Xuan, Yi Kang
2023 J jnl
A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application.
IEEE Trans. Circuits Syst. II Express Briefs
Zihao Xuan, Chang Liu, Yue Zhang, Yuan Li, Yi Kang
2023 J jnl
AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect.
CoRR
Zihao Xuan, Song Chen, Yi Kang
2023 — conf
An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.
BioCAS
Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang
2022 C conf
HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation.
ISCAS
Zihao Xuan, Yue Zhang, Yuan Li, Chang Liu, Yi Kang
2022 J jnl
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Zihao Xuan, Yi Kang
2021 — conf
A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute.
ASICON
Chang Liu, Zihao Xuan, Yi Kang