Zied Marrakchi

84 papers A 5B 2C 3Misc 1Journal 18Unranked 53

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Development and Analysis of Novel Mesh of Tree-based embedded FPGA. J. Supercomput. Hajer Saidi, Mariem Turki, Zied Marrakchi, Mohamed Abid, Abdulfattah Obeid
2022	J	`jnl`	Mesh of Trees FPGA Architecture: Exploration and Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
2021	J	`jnl`	Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework. J. Circuits Syst. Comput. Hajer Saidi, Mariem Turki, Zied Marrakchi, Hela Ben Ahmed, Abdulfattah Obeid, Mohamed Abid
2020	C	`conf`	A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGA. ISDA Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
2020	B	`conf`	Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor. IWCMC Hajer Saidi, Mariem Turki, Zied Marrakchi, Abdulfattah Obeid, Mohamed Abid
2020	C	`conf`	Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes. AICCSA Hajer Saidi, Mariem Turki, Zied Marrakchi, Abdulfattah Obeid, Mohamed Abid
2019	—	`conf`	Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance. HPCS Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Mohamed Abid, Abdulfattah Obeid
2019	B	`conf`	Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires. IWCMC Khouloud Bouaziz, Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Abdulfattah Mohammad Obeid
2019	—	`conf`	New CAD Tools to ConFigure Tree-Based Embedded FPGA. HPCS Hajer Saidi, Mariem Turki, Zied Marrakchi, M. S. Ben Saleh, Mohamed Abid
2017	—	`conf`	On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
2017	J	`jnl`	Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
2016	—	`conf`	Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
2016	—	`conf`	Embedded FPGA accelerator for Wireless Sensor Network nodes. IDT Hajer Saidi, Mariem Turki, Zied Marrakchi, Mohammed S. BenSaleh, Mohamed Abid
2016	C	`conf`	Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid
2016	J	`jnl`	Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
2016	—	`conf`	Rebuilding synthesized design hierarchy based on instances path names of flattened netlist. IDT Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid
2016	—	`conf`	The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez
2016	—	`conf`	Tutorial 2: "Challenges of FPGA-based prototyping & debugging". IDT Zied Marrakchi, Eman El Mandouh
2015	J	`jnl`	Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro Vinod Pangracious, Zied Marrakchi, Habib Mehrez
2015	J	`jnl`	H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Comput. Digit. Tech. Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
2015	—	`conf`	Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid
2015	J	`jnl`	Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Des. Autom. Embed. Syst. Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
2015	—	`book`	Three-Dimensional Design Methodologies for Tree-based FPGA Architecture Vinod Pangracious, Zied Marrakchi, Habib Mehrez
2014	J	`jnl`	A Top-Down Optimization Methodology for Mutually Exclusive Applications. Int. J. Reconfigurable Comput. Alp Kiliç, Zied Marrakchi, Habib Mehrez
2014	J	`jnl`	Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
2014	—	`conf`	Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq
2014	—	`conf`	Flexible reconfigurable architecture for DSP applications. SoCC Abdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid
2014	—	`conf`	Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
2014	J	`jnl`	MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. Int. J. Embed. Real Time Commun. Syst. Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez
2014	Misc	`conf`	MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. ATSIP Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez
2014	—	`conf`	On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi
2014	—	`conf`	Power consumption analysis for mesh based FPGA. DTIS Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez
2014	—	`conf`	Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez
2014	A	`conf`	Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang
2013	—	`conf`	A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips Vinod Pangracious, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez
2013	—	`conf`	Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. SSD Nidhameddine Belhadj, Nejmeddine Bahri, Mohamed Ali Ben Ayed, Zied Marrakchi, Habib Mehrez
2013	—	`conf`	Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT Vinod Pangracious, Zied Marrakchi, Habib Mehrez
2013	—	`conf`	Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS Vinod Pangracious, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC Vinod Pangracious, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi
2013	J	`jnl`	Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq
2013	J	`jnl`	Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Int. J. Reconfigurable Comput. Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
2013	—	`conf`	High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi
2013	J	`jnl`	Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. Emna Amouri, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
2013	—	`conf`	New synthesis approach of hierarchical benchmarks for hardware prototyping. DTIS Mariem Turki, Zied Marrakchi, Mohamed Abid
2013	—	`conf`	Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. ISSoC Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid
2013	—	`conf`	Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez
2013	—	`conf`	Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi
2013	—	`conf`	TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT Vinod Pangracious, Habib Mehrez, Zied Marrakchi
2012	—	`conf`	A logic sharing synthesis tool for mutually exclusive applications. DTIS Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez
2012	J	`jnl`	A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
2012	—	`conf`	Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig Mariem Turki, Habib Mehrez, Zied Marrakchi
2011	J	`jnl`	Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez
2011	—	`conf`	Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
2011	—	`conf`	Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC Emna Amouri, Zied Marrakchi, Habib Mehrez
2011	J	`jnl`	Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
2010	—	`conf`	Application Specific FPGA Using Heterogeneous Logic Blocks. ARC Husain Parvez, Zied Marrakchi, Habib Mehrez
2010	—	`conf`	Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS Emna Amouri, Zied Marrakchi, Habib Mehrez
2010	—	`conf`	Exploration of Heterogeneous FPGA Architectures. ReCoSoC Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez
2010	A	`conf`	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA Husain Parvez, Zied Marrakchi, Habib Mehrez
2010	—	`conf`	On the optimization of FPGA area depending on target applications. APCCAS Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi
2010	—	`conf`	Routability driven placement for mesh-based FPGA architecture. IDT Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez
2009	—	`conf`	ASIF: Application Specific Inflexible FPGA. FPT Husain Parvez, Zied Marrakchi, Habib Mehrez
2009	J	`jnl`	FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez
2009	—	`conf`	Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
2009	—	`conf`	Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez
2008	—	`conf`	A new coarse-grained FPGA architecture exploration environment. FPT Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez
2008	—	`conf`	Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez
2008	—	`conf`	Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig Husain Parvez, Zied Marrakchi, Habib Mehrez
2008	—	`—`	Exploration and optimization of tree-based FPGA architectures. (Exploration et optimisation d'architectures FPGA arborescentes). Zied Marrakchi
2008	—	`conf`	The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez
2007	—	`conf`	Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
2007	—	`conf`	Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
2006	A	`conf`	A multilevel hierarchical interconnection structure for FPGA. FPGA Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
2006	—	`conf`	A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI Zied Marrakchi, Hayder Mrabet, Habib Mehrez
2006	A	`conf`	Configuration tools for a new multilevel hierarchical FPGA. FPGA Zied Marrakchi, Hayder Mrabet, Habib Mehrez
2006	—	`conf`	Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot
2006	A	`conf`	Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
2005	—	`conf`	Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig Zied Marrakchi, Hayder Mrabet, Habib Mehrez
2005	—	`conf`	Implementation of Scalable Embedded FPGA for SOC. ReCoSoC Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot