Zia Abbas - RankMe

75 papers A 2C 25Misc 8Journal 18Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	Adaptive Control Strategies in DC-DC Converter for Improved Transient Response and Efficiency for High Load Slew and Fast Switching Loops. VLSID Bharadwaj Subramaniam, Zia Abbas
2026	Misc	`conf`	LeakAnalyser: Uncertainty-Aware Analysis of Leakage Power in Digital Circuits Under PVT Variations. VLSID Sarang Kudtarkar, Zia Abbas
2026	Misc	`conf`	PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells. VLSID Mohammad Rehan Akhtar, Zia Abbas
2026	J	`jnl`	RelOps: Reliability Optimization in Standard Cells Across PVT Variations in FinFET Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammad Rehan Akhtar, Ritwik Basyas Goswami, Zia Abbas
2025	C	`conf`	A bidirectional frequency detector independent of input transition density for a wide-tuning range applications. ISCAS Abhinav Vajrala, Rajesh Mahadev, Santosh Yachareni, Zia Abbas
2025	J	`jnl`	Artificial intelligence in globesity research: diagnosis, treatment, and prevention solutions for a healthier world with future recommendations. Int. J. Syst. Assur. Eng. Manag. Farwa Munir, Hitesh Chopra, Muhammad Hassan Nasir, L. V. Simhachalam, Zainab Bintay Anis, Shahar Bano, Nida Islam, Atif Amin Baig, Md Belal Bin Heyat, Saba Parveen, Mohamed Bahri, Zia Abbas
2025	C	`conf`	C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs. ISCAS Ritwik Basyas Goswami, Mohammad Rehan Akhtar, Andleeb Zahra, Zia Abbas
2025	Misc	`conf`	Low-Power Voltage Reference: Review & Progress. VTS Abhishek Pullela, Ashfakh Huluvallay, Arpan Jain, Zia Abbas, Inhee Lee
2025	J	`jnl`	Randomized processes to create diverse models for One-class classifier ensembles. Appl. Soft Comput. Deepthi Amuru, Amir Ahmad, Zia Abbas
2025	C	`conf`	Towards Designing a Unified DNN Architecture for Analog and Mixed-Signal Circuit Characterization. ISCAS Deepthi Amuru, Chetan Mittal, Zia Abbas
2025	C	`conf`	Zero-shot Learning in Performance Prediction of Digital VLSI Circuits. ISCAS Deepthi Amuru, Zia Abbas
2024	—	`conf`	A 0.6V, 13nW, 0.0012%/V Line Sensitivity PVT - Invariant Voltage Reference Without Using Resistors and Amplifiers. MWSCAS Chetan Mittal, Jalluri Ramgopal, Khanh M. Le, Zia Abbas
2024	Misc	`conf`	A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications. VLSID Chetan Mittal, Arnab Dey, Anubhab Banerjee, Ashfakh Ali, Zia Abbas
2024	J	`jnl`	A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of -55 to 100 °C without using amplifiers and resistors. Microelectron. J. Bhartipudi Sahishnavi, Arnab Dey, Anubhab Banerjee, Andleeb Zahra, Zia Abbas
2024	—	`conf`	A Process and Temperature Compensation Technique for Ring-VCO in Charge-Pump PLL. MWSCAS Mehul Kumar Saraswat, Rajesh Mahadev, Shameer Basha Yerragudi, Khanh M. Le, Zia Abbas
2024	C	`conf`	A Single-Point, Auto-Calibration Technique For PTAT/CTAT Resistance Based Current References. ISCAS Arpan Jain, Ashfakh Ali, Dheekshith Akula, Abhishek Pullela, Zia Abbas
2024	J	`jnl`	A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles. J. Inf. Knowl. Manag. Amir Ahmad, Sami M. Halawani, Ajay Kumar, Arshad Hashmi, Mutasem Jarrah, Abdul Rafey Ahmad, Zia Abbas
2024	—	`conf`	A Trim-Free PVT Invariant Current Reference with 0.48% Process Inaccuracy Using VTH Tracking Approach. MWSCAS Vishnu Kuncham, Jalluri Ram Gopal, V. S. S. Pradhith, Aniketh Atmakuri, Chetan Mittal, Khanh M. Le, Zia Abbas
2024	C	`conf`	An inductor-less, cost-effective On-chip CMOS VNA for bio-molecule detection. ISCAS Bhartipudi Sahishnavi, Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Andleeb Zahra, Prabhakar Bhimalapuram, Syed Azeemuddin, Zia Abbas
2024	—	`conf`	Design and Optimization of Robust Process Monitors. MWSCAS Shiva Sharma, Koushik De, Bhartipudi Sahishnavi, Khanh M. Le, Zia Abbas
2024	C	`conf`	Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation. ISCAS Prasha Srivastava, Pawan Kumar, Zia Abbas
2024	C	`conf`	MetaCirc: A Meta-learning Approach for Statistical Leakage Estimation Improvement in Digital Circuits. ISCAS Nouduru Venkata Raghavendra, Deepthi Amuru, Zia Abbas
2024	J	`jnl`	Qualitative data augmentation for performance prediction in VLSI circuits. Integr. Prasha Srivastava, Pawan Kumar, Zia Abbas
2024	J	`jnl`	Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation. ACM Trans. Design Autom. Electr. Syst. Deepthi Amuru, Raja Mavullu Vechalapu, Zia Abbas
2023	C	`conf`	A 0.5V, pico-watt, 0.06%/V / 0.03%/V low supply sensitive current/voltage reference without using amplifiers and resistors. ISCAS Bhartipudi Sahishnavi, Sampath Kumar, Ashfakh Ali, Arnab Dey, Inhee Lee, Zia Abbas
2023	C	`conf`	A 162nW, 0.845pJ/step Resistance-to-Digital Converter for Miniature Battery-Powered Sensing Systems. ISCAS Arnab Dey, Inhee Lee, Ashfakh Ali, Arpan Jain, Abhishek Pullela, Zia Abbas
2023	C	`conf`	A 2.3nW Gate-Leakage Based Sub-Bandgap Voltage Reference with Line Sensitivity of 0.0066%/V from -40°C to 150°C for Low-Power IoT Systems. ISCAS Arnab Dey, Bharadwaj Subramaniam, Ashfakh Ali, Bhartipudi Sahishnavi, Abhishek Pullela, Zia Abbas
2023	—	`conf`	A 250pA, Gate-Leakage Based Trimming Free Current Reference, from -55°C to 150°C for Lower Power IoT Applications. MWSCAS Abhinav Vajrala, Dheekshith Akula, Arnab Dey, Khanh M. Le, Zia Abbas
2023	—	`conf`	A 37nW, All-in-One Trim-Free Voltage/Current Reference Without Using Resistors and Amplifiers. MWSCAS Chetan Mittal, Arnab Dey, Ashfakh Ali, Khanh M. Le, Zia Abbas
2023	C	`conf`	A 7 nW, 1 kHz, -40-170°C Relaxation Oscillator with Switch-Leakage Compensation for Low-Power High-Temperature IoT Systems. ISCAS Ashfakh Huluvallay, Abhishek Pullela, Ehab A. Hamed, Arpan Jain, Naveen Dasari, Zia Abbas, Inhee Lee
2023	—	`conf`	A High PSRR CMOS Voltage and Current Reference in One Circuit Without Amplifier for Low Power Applications. ICM Ashutosh Pathy, Andleeb Zahra, Amir Ahmad, Zia Abbas
2023	A	`conf`	A Label-Free Low-Cost Radio Frequency Driven Noninvasive Lab-on-Chip System for Creatinine Detection. ICST Swarnim Sinha, Andleeb Zahra, Imran Siddiqui, Pawan Kumar, Alimpan Modak, Prabhakar Bhimalapuram, Tapan K. Sau, Syed Azeemuddin, Zia Abbas
2023	J	`jnl`	AI/ML algorithms and applications in VLSI design and technology. Integr. Deepthi Amuru, Andleeb Zahra, Harsha V. Vudumula, Pavan K. Cherupally, Sushanth R. Gurram, Amir Ahmad, Zia Abbas
2023	C	`conf`	An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications. ISCAS Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Inhee Lee, Zia Abbas
2023	J	`jnl`	Approximate Toom-Cook FFT with sparsity aware error tuning in a shared memory architecture. Integr. Mohammed Salman Ahmed, Md. Kalesha, Andleeb Zahra, Zia Abbas
2023	—	`conf`	Design and Analysis of Low Power 20 GHz Colpitts VCO with FoM of 196.26 dBc/Hz. MWSCAS Srayan Sankar Chatterjee, Arpit Sahni, Harikrishna Kambham, Zia Abbas, Abhishek Srivastava
2023	A	`conf`	Design and Fabrication of Microfluidic Chip for Temperature Control Applications in Biomedical. ICST Andleeb Zahra, Giampiero de Cesare, Domenico Caputo, Nicola Lovecchio, Prabhakar Bhimalapuram, Syed Azeemuddin, Zia Abbas
2023	—	`conf`	Design of Approximate Full Adders for Error Resilient Applications. ICCA Deepthi Amuru, Andleeb Zahra, Varnika Karakuram, Zia Abbas
2023	J	`jnl`	Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation. CoRR Prasha Srivastava, Pawan Kumar, Zia Abbas
2023	J	`jnl`	Qualitative Data Augmentation for Performance Prediction in VLSI circuits. CoRR Prasha Srivastava, Pawan Kumar, Zia Abbas
2022	C	`conf`	A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems. ISCAS Abhishek Pullela, Ashfakh Ali, Arpan Jain, Inhee Lee, Zia Abbas
2022	Misc	`conf`	A 180 VLSID Arpan Jain, Abhishek Pullela, Ashfakh Ali, Zia Abbas
2022	J	`jnl`	A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications. IEEE Trans. Circuits Syst. II Express Briefs Samriddhi Agarwal, Ashutosh Pathy, Zia Abbas
2022	J	`jnl`	AI/ML Algorithms and Applications in VLSI Design and Technology. CoRR Deepthi Amuru, Harsha V. Vudumula, Pavan K. Cherupally, Sushanth R. Gurram, Amir Ahmad, Andleeb Zahra, Zia Abbas
2022	—	`conf`	Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits. VLSI-DAT Kushagra Agarwal, Aryamaan Jain, Deepthi Amuru, Zia Abbas
2022	J	`jnl`	Implementation of TRNG with SHA-3 for hardware security. Microelectron. J. Annapurna Kamadi, Zia Abbas
2021	—	`conf`	A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications. MWSCAS Ashutosh Pathy, Adithya Banthi, Zia Abbas
2021	C	`conf`	A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems. ISCAS Abhishek Pullela, Ashfakh Ali, Arpan Jain, Adithya Banthi, Zia Abbas
2021	—	`conf`	A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications. MWSCAS Abhishek Pullela, Ashfakh Ali, Sushanth Reddy, Arpan Jain, Zia Abbas
2021	C	`conf`	Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. ISCAS Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas
2021	C	`conf`	Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. ISCAS Prasenjit Saha, Salman Ahmed, Hema Sai Kalluru, Zia Abbas
2021	—	`conf`	PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits. ISQED Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas
2021	Misc	`conf`	Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. VLSID Prasenjit Saha, Hema Sai Kalluru, Zia Abbas
2020	Misc	`conf`	3.75ppm/ VLSID Mounika Kelam, Balaji Yadav Battu, Zia Abbas
2020	C	`conf`	67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications. ISCAS Balaji Yadav Battu, Mounika Kelam, Adithya Bathi, Zia Abbas
2020	—	`conf`	A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator. ISVLSI Mounika Kelam, Balaji Yadav Battu, Zia Abbas
2020	—	`conf`	A Sub-nW, 8T Current Reference Consuming Constant Power w.r.t Process & Temperature. MWSCAS Ashfakh Ali, Abhishek Pullela, Arpan Jain, Zia Abbas
2020	C	`conf`	ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications. ISCAS Mohammed Salman Ahmed, Deepthi Amuru, Zia Abbas
2020	C	`conf`	An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells. ISCAS Deepthi Amuru, Mohammed Salman Ahmed, Zia Abbas
2020	C	`conf`	Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance. ISCAS Balaji Yadav Battu, Mounika Kelam, Koushik De, Zia Abbas
2019	C	`conf`	A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications. VLSI-SoC Ashfakh Ali, Sai Kiran, Arpan Jain, Zia Abbas
2019	C	`conf`	A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications. ISCAS Arpan Jain, Ashfakh Ali, Sai Kiran, Zia Abbas
2019	—	`conf`	A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits. APCCAS Shirisha Gourishetty, Harshini Mandadapu, Andleeb Zahra, Zia Abbas
2019	C	`conf`	A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design. ICCD Mohammed Salman Ahmed, Zia Abbas
2019	C	`conf`	PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design. ISCAS Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas
2019	—	`conf`	Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms. ISQED Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas
2019	—	`conf`	Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models. VDAT Deepthi Amuru, Andleeb Zahra, Zia Abbas
2018	—	`conf`	LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. VDAT Zia Abbas, Andleeb Zahra, Mauro Olivieri
2018	—	`conf`	Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power. VDAT Prateek Gupta, Shubham Kumar, Zia Abbas
2018	—	`conf`	Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier. VDAT Ashfakh Ali, Arpan Jain, Zia Abbas
2016	J	`jnl`	Optimal transistor sizing for maximum yield in variation-aware standard cell design. Int. J. Circuit Theory Appl. Zia Abbas, Mauro Olivieri
2014	J	`jnl`	A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. Zia Abbas, Antonio Mastrandrea, Mauro Olivieri
2014	J	`jnl`	Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. Microelectron. J. Zia Abbas, Mauro Olivieri
2013	J	`jnl`	Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+). Microelectron. J. Zia Abbas, Mauro Olivieri, Marat Yakupov, Andreas Ripp
2012	—	`conf`	Yield optimization for low power current controlled current conveyor. SBCCI Zia Abbas, Marat Yakupov, Mauro Olivieri, Andreas Ripp, Gunter Strube