Zhuolun He

54 papers A* 8A 11B 1C 1Misc 1Journal 21Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
CombRewriter: Enabling Combinational Logic Simplification in MLIR-Based Hardware Compiler.
ASP-DAC
Haisheng Zheng, Zhuolun He, Shuo Yin, Yuzhe Ma, Bei Yu
2026 — conf
Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective.
ISPD
Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, Bei Yu
2026 J jnl
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst.
Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 J jnl
Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table.
CoRR
Haoyuan Wu, Haisheng Zheng, Shoubo Hu, Zhuolun He, Bei Yu
2025 A* conf
ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script Customization.
DAC
Haisheng Zheng, Haoyuan Wu, Zhuolun He
2025 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu
2025 — conf
Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation.
NAACL (Long Papers)
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation.
CoRR
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling.
ACM Trans. Design Autom. Electr. Syst.
Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu
2025 — conf
Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts.
ACL (1)
Haoyuan Wu, Rui Ming, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts.
CoRR
Haoyuan Wu, Rui Ming, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, Bei Yu
2025 A conf
GPU Acceleration for Versatile Buffer Insertion.
ICCAD
Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025 — conf
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
ISPD
Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025 J jnl
IncreMacro: Incremental Macro Placement Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2025 J jnl
Large Language Models for EDA: From Assistants to Agents.
Found. Trends Electron. Des. Autom.
Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, Bei Yu
2025 J jnl
Large Language Models for EDA: Future or Mirage?
ACM Trans. Design Autom. Electr. Syst.
Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu
2025 A conf
MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation.
ICCAD
Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu
2025 J jnl
On-Policy Optimization with Group Equivalent Preference for Multi-Programming Language Understanding.
CoRR
Haoyuan Wu, Rui Ming, Jilong Gao, Hangyu Zhao, Xueyi Chen, Yikai Yang, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
One-Token Rollout: Guiding Supervised Fine-Tuning of LLMs with Policy Gradient.
CoRR
Rui Ming, Haoyuan Wu, Shoubo Hu, Zhuolun He, Bei Yu
2025 A* conf
Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction.
DAC
Hang Liu, Hao Geng, Zhuolun He, Qi Sun, Cheng Zhuo
2025 J jnl
ToTRL: Unlock LLM Tree-of-Thoughts Reasoning Potential through Puzzles Solving.
CoRR
Haoyuan Wu, Xueyi Chen, Rui Ming, Jilong Gao, Shoubo Hu, Zhuolun He, Bei Yu
2025 J jnl
UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings.
CoRR
Jiajun Qin, Yuan Pu, Zhuolun He, Seunggeun Kim, David Z. Pan, Bei Yu
2025 A conf
iRw: An Intelligent Rewriting.
DATE
Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, Bei Yu
2024 A conf
CBTune: Contextual Bandit Tuning for Logic Synthesis.
DATE
Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu
2024 J jnl
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2024 A conf
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
ICCAD
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
CoRR
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 — conf
IncreMacro: Incremental Macro Placement Refinement.
ISPD
Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2024 B conf
LSTP: A Logic Synthesis Timing Predictor.
ASPDAC
Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu
2024 — conf
Large Language Models for EDA: Future or Mirage?
ISPD
Zhuolun He, Bei Yu
2024 A* conf
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
DAC
Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024 A* conf
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry.
DAC
Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu
2024 A* conf
Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks.
EMNLP
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2024 — conf
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ISPD
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 A conf
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search.
ICCAD
Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu
2023 A* conf
AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution.
AAAI
Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu
2023 — conf
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
MLCAD
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2023 J jnl
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
CoRR
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2023 J jnl
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu
2023 A conf
Efficient Design Rule Checking with GPU Acceleration.
DATE
Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu
2023 J jnl
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie
2023 A conf
Invited Paper: Heterogeneous Acceleration for Design Rule Checking.
ICCAD
Zhuolun He, Bei Yu
2023 A* conf
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration.
DAC
Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu
2022 A* conf
Functionality matters in netlist representation learning.
DAC
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang
2022 A conf
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms.
ICCAD
Zhuolun He, Yuzhe Ma, Bei Yu
2021 A conf
Graph Learning-Based Arithmetic Block Identification.
ICCAD
Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu
2021 — conf
Physical Synthesis for Advanced Neural Network Processors.
ASP-DAC
Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu
2020 J jnl
Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains.
IEEE Trans. Neural Networks Learn. Syst.
Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, Ngai Wong
2020 J jnl
HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression.
CoRR
Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, Ngai Wong
2020 C conf
Learn to Floorplan through Acquisition of Effective Local Search Heuristics.
ICCD
Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong
2020 — conf
Understanding Graphs in EDA: From Shallow to Deep Learning.
ISPD
Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu
2018 Misc conf
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos.
FCCM
Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, Guojie Luo
2017 A conf
FPGA Acceleration for Computational Glass-Free Displays.
FPGA
Zhuolun He, Guojie Luo