Zhuo Li - RankMe

81 papers A* 12A 18Misc 2Journal 20Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Invited: The Future of Functional ECO Automation and Logical Equivalence Checking for Advanced Digital Design Flows. ISPD Zhuo Li, David Stratman
2020	J	`jnl`	Conference Report From The 57th Design Automation Conference. IEEE Des. Test Zhuo Li
2018	J	`jnl`	MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2018	—	`conf`	Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
2017	J	`jnl`	Stitch aware detailed placement for multiple E-beam lithography. Integr. Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	A	`conf`	MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	—	`conf`	Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2015	J	`jnl`	Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
2014	—	`conf`	Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
2014	J	`jnl`	Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2013	A	`conf`	CATALYST: planning layer directives for effective design closure. DATE Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
2013	A	`conf`	Clock power minimization using structured latch templates and decision tree induction. ICCAD Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
2013	A	`conf`	ICCAD-2013 CAD contest in mask optimization and benchmark suite. ICCAD Shayak Banerjee, Zhuo Li, Sani R. Nassif
2013	A	`conf`	ICCAD-2013 CAD contest in placement finishing and benchmark suite. ICCAD Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert
2013	A*	`conf`	Routing congestion estimation with real design constraints. DAC Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
2013	J	`jnl`	Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2013	A	`conf`	The overview of 2013 CAD contest at ICCAD. ICCAD Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan
2012	J	`jnl`	$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuo Li, Nancy Ying Zhou, Weiping Shi
2012	A	`conf`	2012 TAU power grid simulation contest: Benchmark suite and results. ICCAD Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif
2012	A*	`conf`	GLARE: global and local wiring aware routability evaluation. DAC Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2012	A*	`conf`	Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou
2012	A	`conf`	ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	—	`conf`	Keep it straight: teaching placement how to better handle designs with datapaths. ISPD Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2012	A	`conf`	Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li
2012	A	`conf`	Placement: Hot or Not? ICCAD Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward
2012	A*	`conf`	The DAC 2012 routability-driven placement contest and benchmark suite. DAC Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	A*	`conf`	Yield estimation via multi-cones. DAC Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif
2011	A	`conf`	2011 TAU power grid simulation contest: Benchmark suite and results. ICCAD Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif
2011	J	`jnl`	CAD for Gigascale SoC Design and Verification Solutions. VLSI Design Shiyan Hu, Zhuo Li, Yangdong Deng
2011	J	`jnl`	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov
2011	—	`conf`	Quantifying academic placer performance on custom designs. ISPD Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.
2011	J	`jnl`	Shedding Physical Synthesis Area Bloat. VLSI Design Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan
2011	—	`conf`	The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy
2010	A*	`conf`	Detecting tangled logic structures in VLSI netlists. DAC Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn
2010	—	`conf`	ITOP: integrating timing optimization within placement. ISPD Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu
2010	A	`conf`	New placement prediction and mitigation techniques for local routing congestion. ICCAD Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji
2010	—	`conf`	Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou
2010	—	`conf`	What makes a design difficult to route. ISPD Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez
2009	J	`jnl`	A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. IEEE Trans. Circuits Syst. II Express Briefs Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	—	`conf`	A faster approximation scheme for timing driven minimum cost layer assignment. ISPD Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	A*	`conf`	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	—	`conf`	The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi
2008	—	`conf`	A Root-Finding Method for Assessing SRAM Stability. ISQED Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif
2008	A	`conf`	A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD Shiyan Hu, Zhuo Li, Charles J. Alpert
2008	—	`ch.`	Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation Jiang Hu, Zhuo Li, Shiyan Hu
2008	—	`conf`	Fast interconnect synthesis with layer assignment. ISPD Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia
2008	A*	`conf`	Path smoothing via discrete optimization. DAC Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert
2008	A	`conf`	Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
2008	J	`jnl`	RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2008	—	`conf`	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2008	A	`conf`	SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
2007	—	`conf`	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. ASP-DAC Nancy Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu
2007	J	`jnl`	An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types CoRR Zhuo Li, Weiping Shi
2007	J	`jnl`	Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
2007	A*	`conf`	Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. DAC Nancy Ying Zhou, Zhuo Li, Weiping Shi
2007	—	`conf`	Probabilistic Congestion Prediction with Partial Blockages. ISQED Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
2007	J	`jnl`	Techniques for Fast Physical Synthesis. Proc. IEEE Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2007	—	`conf`	The nuts and bolts of physical synthesis. SLIP Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2007	J	`jnl`	Wire Sizing for Non-Tree Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuo Li, Nancy Ying Zhou, Weiping Shi
2006	A	`conf`	A new RLC buffer insertion algorithm. ICCAD Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
2006	—	`conf`	An ASP-DAC Zhuo Li, Weiping Shi
2006	J	`jnl`	An O(bn IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuo Li, Weiping Shi
2006	A*	`conf`	Buffer insertion in large circuits with constructive solution search techniques. DAC Mandar Waghmode, Zhuo Li, Weiping Shi
2006	A*	`conf`	Fast algorithms for slew constrained minimum cost buffering. DAC Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2005	—	`conf`	A More Effective C ISQED Sani R. Nassif, Zhuo Li
2005	J	`jnl`	A fast algorithm for optimal buffer insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weiping Shi, Zhuo Li
2005	A	`conf`	An O(bn DATE Zhuo Li, Weiping Shi
2005	—	`—`	Fast interconnect optimization. Zhuo Li
2005	J	`jnl`	Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2005	—	`conf`	Making fast buffer insertion even faster via approximation techniques. ASP-DAC Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2004	—	`conf`	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	Misc	`conf`	A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
2004	—	`conf`	Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC Weiping Shi, Zhuo Li, Charles J. Alpert
2004	A	`conf`	K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
2004	—	`conf`	Longest path selection for delay test under process variation. ASP-DAC Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	—	`conf`	PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2003	Misc	`conf`	A Circuit Level Fault Model for Resistive Opens and Bridges. VTS Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	J	`jnl`	A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	A*	`conf`	An O(nlogn) time algorithm for optimal buffer insertion. DAC Weiping Shi, Zhuo Li
2003	—	`conf`	CodSim -- A Combined Delay Fault Simulator. DFT Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
2003	—	`conf`	Process variation dimension reduction based on SVD. ISCAS (4) Zhuo Li, Xiang Lu, Weiping Shi