Zhongyuan Zhao

15 papers A* 1A 3B 1C 1Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hanchen Jin, Zichao Yue, Zhongyuan Zhao, Yixiao Du, Chenhui Deng, Nitish Srivastava, Zhiru Zhang
2024 A* conf
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore.
ISCA
Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor
2024 J jnl
UniSparse: An Intermediate Language for General Sparse Format Customization.
CoRR
Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2024 J jnl
UniSparse: An Intermediate Language for General Sparse Format Customization.
Proc. ACM Program. Lang.
Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2023 J jnl
An Intermediate Language for General Sparse Format Customization.
IEEE Comput. Archit. Lett.
Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2022 J jnl
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten
2021 A conf
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.
DATE
Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
2020 J jnl
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.
IEEE Trans. Parallel Distributed Syst.
Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
2019 B conf
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.
ISPASS
Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna
2018 — conf
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.
ReConFig
Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
2018 A conf
Optimizing the data placement and transformation for multi-bank CGRA computing system.
DATE
Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
2017 A conf
A static-placement, dynamic-issue framework for CGRA loop accelerator.
DATE
Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
2016 — conf
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.
FPT
Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
2015 C conf
Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.
PRDC
Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao
2015 — conf
Resource-saving compile flow for coarse-grained reconfigurable architectures.
ReConFig
Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao