Zhongfeng Wang

465 papers A* 3A 7B 6C 72Misc 13Journal 242Unranked 122

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A High-Performance and Hardware-Efficient Iterative Detection and Decoding Receiver for Polar-Coded Massive MIMO System. IEEE Trans. Circuits Syst. I Regul. Pap. Huiyu Feng, Suwen Song, Chuan Zhang, Zhongfeng Wang
2026	J	`jnl`	A High-Speed FPGA Implementation for IVF-PQ Index Construction. IEEE Trans. Circuits Syst. I Regul. Pap. Yifeng Song, Yuan Du, Zhongfeng Wang
2026	—	`conf`	A Precision-Scalable Accelerator for Compressive Hyperspectral Image Reconstruction with a Lightweight DUN. ASP-DAC Shuo Zhang, Shengzhi Qiang, Wendong Mao, Zhongfeng Wang
2026	J	`jnl`	A Scalable Segment-Parallel Architecture for High-Efficiency Lossless Data Compression. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Chen, Suwen Song, Zhongfeng Wang
2026	J	`jnl`	APT-LLM: Exploiting Arbitrary-Precision Tensor Core Computing for LLM Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang
2026	J	`jnl`	WiFlow: A Precision-Scalable DNN Training Accelerator Through Winograd Algorithm and Dataflow Co-Design. IEEE Trans. Circuits Syst. I Regul. Pap. Hui Wang, Jinming Lu, Rui Ding, Weize Ma, Zhongfeng Wang, Jun Lin
2025	J	`jnl`	A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline. ACM Trans. Design Autom. Electr. Syst. Yuefei Wang, Wendong Mao, Lang Feng, Jin Sha, Zhongfeng Wang
2025	C	`conf`	A High-Speed 8-bit Single-Channel SAR ADC with Tailored Bit Intervals. ISCAS Xinyu Li, Ruida Wang, Mengying Zhang, Congyi Zhu, Zhongfeng Wang, Jun Lin
2025	—	`conf`	A Low-Complexity Soft-Output MLSE Equalizer with DFE-Assisted State Reduction. SiPS Peng Zhang, Changfu He, Zhongfeng Wang, Suwen Song
2025	—	`conf`	A Low-Complexity XOR-Based BCH Decoder for PAM4 Modulation Systems. ISVLSI Changfu He, Xinle Jia, Yuxing Chen, Wenli Xu, Suwen Song, Zhongfeng Wang
2025	J	`jnl`	A Low-Complexity and High-Throughput Hardware Design for Lempel-Ziv 4 Compression Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Chen, Suwen Song, Zhongfeng Wang
2025	J	`jnl`	A Memory-Efficient Framework for Deformable Transformer with Neural Architecture Search. CoRR Wendong Mao, Mingfan Zhao, Jianfeng Guan, Qiwei Dong, Zhongfeng Wang
2025	J	`jnl`	A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. Meng Guo, Qi Wu, Chuanning Wang, Yangcan Zhou, Shaowei Wang, Chuan Zhang, Zhongfeng Wang, Jun Lin
2025	J	`jnl`	A Unified Accelerator for All-in-One Image Restoration Based on Prompt Degradation Learning. IEEE Trans. Circuits Syst. I Regul. Pap. Siyu Zhang, Qiwei Dong, Wendong Mao, Zhongfeng Wang
2025	J	`jnl`	APT-LLM: Exploiting Arbitrary-Precision Tensor Core Computing for LLM Acceleration. CoRR Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang
2025	J	`jnl`	ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transformers. IEEE Trans. Very Large Scale Integr. Syst. Haikuo Shao, Zhongfeng Wang
2025	J	`jnl`	AccLLM: Accelerating Long-Context LLM Inference Via Algorithm-Hardware Co-Design. CoRR Yanbiao Liang, Huihong Shi, Haikuo Shao, Zhongfeng Wang
2025	J	`jnl`	An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN. IEEE Trans. Circuits Syst. II Express Briefs Haonan Zhang, Siyu Zhang, Wendong Mao, Zhongfeng Wang
2025	J	`jnl`	An Efficient FPGA Implementation of Approximate Nearest Neighbor Search. IEEE Trans. Very Large Scale Integr. Syst. Yifeng Song, Chenjie Liu, Rongrong Zhang, Danyang Zhu, Zhongfeng Wang
2025	J	`jnl`	An Efficient Layer Normalization Training Module With Dynamic Quantization for Transformers. IEEE Trans. Circuits Syst. II Express Briefs Haikuo Shao, Aotao Wang, Zhongfeng Wang
2025	J	`jnl`	An Efficient Sparse Hardware Accelerator for Spike-Driven Transformer. CoRR Zhengke Li, Wendong Mao, Siyu Zhang, Qiwei Dong, Zhongfeng Wang
2025	C	`conf`	An Efficient Training Architecture for Nonlinear Softmax Function in Transformers. ISCAS Haikuo Shao, Zhongfeng Wang
2025	J	`jnl`	An Efficient Window-Based Vision Transformer Accelerator via Mixed-Granularity Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. Qiwei Dong, Siyu Zhang, Zhongfeng Wang
2025	J	`jnl`	An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Dingyang Zou, Gaoche Zhang, Xu Zhang, Meiqi Wang, Zhongfeng Wang
2025	J	`jnl`	An Energy-Efficient FPGA Accelerator for Swin Transformer. IEEE Trans. Very Large Scale Integr. Syst. Yuefei Wang, Wendong Mao, Huihong Shi, Jin Sha, Zhongfeng Wang
2025	J	`jnl`	An Energy-Efficient Neuromorphic Accelerator Based on Deformable Spiking Transformer for Dynamic Vision Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. Haonan Zhang, Siyu Zhang, Wendong Mao, Zhongfeng Wang
2025	—	`conf`	An MIP-based Force-directed Large Scale Placement Refinement Algorithm. ASP-DAC Zewen Li, Ke Tang, Lang Feng, Zhongfeng Wang
2025	A*	`conf`	Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format. HPCA Chao Fang, Man Shi, Robin Geens, Arne Symons, Zhongfeng Wang, Marian Verhelst
2025	J	`jnl`	Block Circulant Adapter for Large Language Models. CoRR Xinyu Ding, Meiqi Wang, Siyu Liao, Zhongfeng Wang
2025	C	`conf`	CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model. ISCAS Jinming Lu, Minghao She, Wendong Mao, Zhongfeng Wang
2025	J	`jnl`	CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model. CoRR Jinming Lu, Minghao She, Wendong Mao, Zhongfeng Wang
2025	J	`jnl`	DATA: A Memory-Efficient Deformable Transformer Accelerator via Neural Architecture Search. IEEE Trans. Very Large Scale Integr. Syst. Mingfan Zhao, Wendong Mao, Zhongfeng Wang
2025	J	`jnl`	DiffAccel: Accelerating Diffusion Models Through Adaptive Feature Optimization and Dynamic Hardware Adaptation. IEEE Trans. Very Large Scale Integr. Syst. Enhao Tang, Weize Ma, Yudan Jiang, Sheng Xu, Zhongfeng Wang, Jun Lin
2025	—	`conf`	Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. ASP-DAC Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang
2025	J	`jnl`	Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing. CoRR Qiong Li, Chao Fang, Longwei Huang, Jun Lin, Zhongfeng Wang
2025	J	`jnl`	Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece. IEEE Trans. Circuits Syst. I Regul. Pap. Haochen Zhang, Xinyuan Qiao, Jing Tian, Suwen Song, Zhongfeng Wang
2025	—	`conf`	FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate Quantization. ISVLSI Aotao Wang, Haikuo Shao, Shaobo Ma, Zhongfeng Wang
2025	J	`jnl`	FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate Quantization. CoRR Aotao Wang, Haikuo Shao, Shaobo Ma, Zhongfeng Wang
2025	J	`jnl`	FlashForge: Ultra-Efficient Prefix-Aware Attention for LLM Decoding. CoRR Zhibin Wang, Rui Ning, Chao Fang, Zhonghui Zhang, Xi Lin, Shaobo Ma, Mo Zhou, Xue Li, Zhongfeng Wang, Chengying Huan, Rong Gu, Kun Yang, Guihai Chen, Sheng Zhong, Chen Tian
2025	J	`jnl`	GEMMV: An LLM-Based Automated Performance-Aware Framework for GEMM Verilog Generation. IEEE J. Emerg. Sel. Topics Circuits Syst. Gaoche Zhang, Dingyang Zou, Kairui Sun, Zhihuan Chen, Meiqi Wang, Zhongfeng Wang
2025	J	`jnl`	HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers. IEEE Trans. Circuits Syst. I Regul. Pap. Xu Zhang, Yaodong Wei, Minghao Li, Jing Tian, Zhongfeng Wang
2025	J	`jnl`	HWSA: A High-Ratio Weight Sparse Accelerator for Efficient CNN Inference. IEEE Trans. Circuits Syst. I Regul. Pap. Xuejing Dai, Jinze Zhang, Zhongfeng Wang, Jun Lin
2025	—	`conf`	High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction. ISVLSI Haoran Pan, Bohang Xiong, Jing Tian, Shikun Zhang, Hao Zhu, Zhongfeng Wang
2025	A	`conf`	LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog Generation. DATE Dingyang Zou, Gaoche Zhang, Kairui Sun, Zhe Wen, Meiqi Wang, Zhongfeng Wang
2025	J	`jnl`	M IEEE Trans. Very Large Scale Integr. Syst. Yanbiao Liang, Huihong Shi, Zhongfeng Wang
2025	J	`jnl`	Memory-Efficient Training with In-Place FFT Implementation. CoRR Xinyu Ding, Bangtian Liu, Siyu Liao, Zhongfeng Wang
2025	J	`jnl`	PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xinrui Wang, Lang Feng, Zhongfeng Wang
2025	J	`jnl`	RETA-AD: A Reconfigurable and Efficient Transformer Accelerator for Autonomous Driving. IEEE Trans. Very Large Scale Integr. Syst. Kairui Sun, Meiqi Wang, Zhongfeng Wang
2025	J	`jnl`	Reduced Complexity Dynamic Schedule for Layered Decoding of LDPC Codes. IEEE Trans. Veh. Technol. Xinle Jia, Yangcan Zhou, Zijian Qin, Jingjing Zhu, Zhongfeng Wang
2025	J	`jnl`	Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks. ACM Trans. Design Autom. Electr. Syst. Xinrui Wang, Lang Feng, Yujie Wang, Taotao Xu, Yinhe Han, Zhongfeng Wang
2025	J	`jnl`	SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. IEEE Trans. Very Large Scale Integr. Syst. Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2025	C	`conf`	SSMA: A Memory-Efficient Accelerator for State Space Model in the Mamba. ISCAS Qiwei Dong, Siyu Zhang, Zhongfeng Wang
2025	J	`jnl`	TAFP-ViT: A Transformer Accelerator via QKV Computational Fusion and Adaptive Pruning for Vision Transformer. ACM Trans. Embed. Comput. Syst. Liang Xu, Hongrui Song, Lan Tian, Zhongfeng Wang, Meiqi Wang
2025	J	`jnl`	Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. Huihong Shi, Haikuo Shao, Wendong Mao, Zhongfeng Wang
2025	—	`conf`	UEDA: A Universal And Efficient Deformable Attention Accelerator For Various Vision Tasks. ASP-DAC Kairui Sun, Meiqi Wang, Junhai Zhou, Zhongfeng Wang
2025	J	`jnl`	VCNPU: An Algorithm-Hardware Co-Optimized Framework for Accelerating Neural Video Compression. IEEE Trans. Very Large Scale Integr. Syst. Siyu Zhang, Wendong Mao, Zhongfeng Wang
2024	A	`conf`	A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network. DATE Siyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang
2024	J	`jnl`	A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. IACR Cryptol. ePrint Arch. Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang
2024	C	`conf`	A Flexible FPGA-Based Accelerator for Efficient Inference of Multi-Precision CNNs. ISCAS Xinyan Liu, Xiao Wu, Haikuo Shao, Zhongfeng Wang
2024	J	`jnl`	A Heterogeneous and Reconfigurable Decoder for the IEEE 1901 Standard. IEEE Trans. Circuits Syst. I Regul. Pap. Yuxing Chen, Zhongfeng Wang
2024	C	`conf`	A High Dynamic Range Feedback Compensation Front-End for Unlimited Sampling ASDM ADC. ISCAS Binqiang Dan, Hui Qian, Zhongfeng Wang
2024	—	`conf`	A High-Speed Implementation of Open FEC Decoder Based on Optimized Storage Strategy. ICCT Xinyuan Qiao, Changfu He, Yuxing Chen, Suwen Song, Zhongfeng Wang
2024	—	`conf`	A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm. SiPS Tao Chen, Suwen Song, Zhongfeng Wang
2024	J	`jnl`	A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm. CoRR Tao Chen, Suwen Song, Zhongfeng Wang
2024	J	`jnl`	A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO. IEEE Trans. Very Large Scale Integr. Syst. Baoling Hong, Haikuo Shao, Zhongfeng Wang
2024	J	`jnl`	A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance. IEEE Trans. Circuits Syst. I Regul. Pap. Jinjie Hu, Suwen Song, Zhongfeng Wang
2024	C	`conf`	A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance. ISCAS Jinjie Hu, Suwen Song, Zhongfeng Wang
2024	—	`conf`	A Precision-Scalable Energy-Efficient DNN Accelerator for Robotic Grasping. APCCAS Zixiong Feng, Zhongfeng Wang, Wendong Mao
2024	B	`conf`	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. ASPDAC Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang
2024	C	`conf`	A Precision-Scalable Vision Accelerator for Robotic Applications. ISCAS Haoran Zeng, Wendong Mao, Siyu Zhang, Zhongfeng Wang
2024	C	`conf`	A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ISCAS Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	J	`jnl`	A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	J	`jnl`	ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu
2024	J	`jnl`	Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. IEEE Trans. Very Large Scale Integr. Syst. Xiao Wu, Miaoxin Wang, Jun Lin, Zhongfeng Wang
2024	—	`conf`	An Automated Hardware Design Framework for Various DNNs Based on ChatGPT. SOCC Qiuhao Zeng, Yuefei Wang, Zhongfeng Wang, Wendong Mao
2024	C	`conf`	An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. ISCAS Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang
2024	J	`jnl`	An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. CoRR Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang
2024	C	`conf`	An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT. ISCAS Haikuo Shao, Huihong Shi, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT. CoRR Haikuo Shao, Huihong Shi, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format. CoRR Chao Fang, Man Shi, Robin Geens, Arne Symons, Zhongfeng Wang, Marian Verhelst
2024	C	`conf`	BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. ISCAS Yuhao Ji, Chao Fang, Zhongfeng Wang
2024	J	`jnl`	BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. CoRR Yuhao Ji, Chao Fang, Zhongfeng Wang
2024	J	`jnl`	CSI-Based MIMO Indoor Positioning Using Attention-Aided Deep Learning. IEEE Commun. Lett. Rongjie Wan, Yuxing Chen, Suwen Song, Zhongfeng Wang
2024	A	`conf`	Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. ICCAD Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang
2024	J	`jnl`	Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. CoRR Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang
2024	J	`jnl`	Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Yangyang Chen, Huiyu Feng, Suwen Song, Zhongfeng Wang
2024	J	`jnl`	Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. CoRR Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang
2024	J	`jnl`	Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang
2024	J	`jnl`	Efficient Soft-Cancellation Flip Decoding of Polar Codes. IEEE Commun. Lett. Yangcan Zhou, Zijian Qin, Zhongfeng Wang
2024	B	`conf`	Efficient Soft-Output List Decoding of Polar Codes for Iterative Detection and Decoding in MIMO System. PIMRC Huiyu Feng, Suwen Song, Zhongfeng Wang
2024	J	`jnl`	GS-MDC: High-Speed and Area-Efficient Number Theoretic Transform Design. IEEE Trans. Circuits Syst. II Express Briefs Yue Geng, Xiao Hu, Zhongfeng Wang
2024	C	`conf`	HSViT: A Hardware and Software Collaborative Design for Vision Transformer via Multi-level Compression. ISCAS Hongrui Song, Liang Xu, Ya Wang, Xiao Wu, Meiqi Wang, Zhongfeng Wang
2024	J	`jnl`	Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Wendong Mao, Meiqi Wang, Xiaoru Xie, Xiao Wu, Zhongfeng Wang
2024	J	`jnl`	Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection. IEEE Internet Things J. Xuewen He, Yichuan Bai, Yujia Liu, Li Du, Zhongfeng Wang, Yuan Du
2024	J	`jnl`	Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins. ACM Trans. Design Autom. Electr. Syst. Ke Tang, Lang Feng, Zhongfeng Wang
2024	J	`jnl`	NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Huihong Shi, Yang Xu, Yuefei Wang, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	NASH: Neural Architecture and Accelerator Search for Multiplication-Reduced Hybrid Models. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Xu, Huihong Shi, Zhongfeng Wang
2024	J	`jnl`	P CoRR Huihong Shi, Xin Cheng, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	P IEEE Trans. Very Large Scale Integr. Syst. Huihong Shi, Xin Cheng, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender. IEEE Trans. Computers Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang
2024	J	`jnl`	RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices. IEEE Trans. Computers Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang
2024	C	`conf`	Reformulated Euclidean Algorithm and Optimized (OREA) Architecture for Reed-Solomon Decoding. ISITA Chao Chen, Zhongfeng Wang, Yunghsiang S. Han, Baoming Bai
2024	J	`jnl`	SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	B	`conf`	SWAT: An Efficient Swin Transformer Accelerator Based on FPGA. ASPDAC Qiwei Dong, Xiaoru Xie, Zhongfeng Wang
2024	J	`jnl`	TECO: A Unified Feature Map Compression Framework Based on Transform and Entropy. IEEE Trans. Neural Networks Learn. Syst. Yubo Shi, Meiqi Wang, Tianyu Cao, Jun Lin, Zhongfeng Wang
2024	J	`jnl`	Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer. CoRR Huihong Shi, Haikuo Shao, Wendong Mao, Zhongfeng Wang
2024	J	`jnl`	WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. IEEE Trans. Circuits Syst. I Regul. Pap. Jinming Lu, Hui Wang, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lang Feng, Jin Sha, Zhongfeng Wang
2023	J	`jnl`	3.8-Gbps Polar Belief Propagation Decoder on GPU. IEEE Commun. Lett. Yuxing Chen, Xinyuan Qiao, Keyue Deng, Suwen Song, Zhongfeng Wang
2023	J	`jnl`	A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network. CoRR Siyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang
2023	J	`jnl`	A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. IEEE Trans. Circuits Syst. I Regul. Pap. Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang
2023	J	`jnl`	A Low-Latency Framework With Algorithm-Hardware Co-Optimization for 3-D Point Cloud. IEEE Trans. Circuits Syst. II Express Briefs Yue Yu, Wendong Mao, Jiapeng Luo, Zhongfeng Wang
2023	J	`jnl`	A New ACD-OMP Accelerator With Clustered Computing Look-Ahead. IEEE Trans. Very Large Scale Integr. Syst. Rongrong She, Hui Qian, Zhongfeng Wang
2023	J	`jnl`	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. CoRR Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	A Unified Acceleration Solution Based on Deformable Network for Image Pixel Processing. IEEE Trans. Circuits Syst. II Express Briefs Wendong Mao, Ziqi Su, Jiapeng Luo, Zhongfeng Wang
2023	J	`jnl`	AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang
2023	J	`jnl`	An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes. IEEE Commun. Lett. Shangpeng Deng, Zhiyuan Xiao, Jin Sha, Zhongfeng Wang
2023	J	`jnl`	An Efficient Accelerator Based on Lightweight Deformable 3D-CNN for Video Super-Resolution. IEEE Trans. Circuits Syst. I Regul. Pap. Siyu Zhang, Wendong Mao, Zhongfeng Wang
2023	—	`conf`	An Efficient Hardware Design for Fast Implementation of HQC. SOCC Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
2023	J	`jnl`	An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. IEEE Trans. Very Large Scale Integr. Syst. Yangyang Chen, Suwen Song, Zhongfeng Wang, Jun Lin
2023	J	`jnl`	An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. Haikuo Shao, Jinming Lu, Meiqi Wang, Zhongfeng Wang
2023	—	`conf`	An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. ISVLSI Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	Automatic Model-Based Dataset Generation for High-Level Vision Tasks of Autonomous Driving in Haze Weather. IEEE Trans. Ind. Informatics Meiqi Wang, Tianqi Su, Siyi Chen, Wenhan Yang, Jiaying Liu, Zhongfeng Wang
2023	Misc	`conf`	Bebert: Efficient And Robust Binary Ensemble Bert. ICASSP Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang
2023	A	`conf`	CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks. DATE Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang
2023	—	`conf`	Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes. ISVLSI Changfu He, Keyue Deng, Suwen Song, Zhongfeng Wang
2023	J	`jnl`	Dual-Bit-Wise Stochastic Decoding for Polar Codes. IEEE Trans. Signal Process. Suwen Song, Lu Liu, Zhongfeng Wang, Juyan Xu
2023	J	`jnl`	ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization. IEEE Trans. Neural Networks Learn. Syst. Jinming Lu, Chao Ni, Zhongfeng Wang
2023	—	`conf`	Efficient Decryption Architecture for Classic McEliece. ISQED Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang
2023	C	`conf`	Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications. ISCAS Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang
2023	J	`jnl`	Efficient N: M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. CoRR Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang
2023	J	`jnl`	FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm. IEEE Trans. Neural Networks Learn. Syst. Wendong Mao, Peixiang Yang, Zhongfeng Wang
2023	J	`jnl`	Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation. IEEE Trans. Circuits Syst. II Express Briefs Lun Ou, Danyang Zhu, Jing Tian, Zhongfeng Wang
2023	J	`jnl`	Fast Successive-Cancellation Decoding of 5G Parity-Check Polar Codes. IEEE Commun. Lett. Yangcan Zhou, Yaojie Zheng, Zhongfeng Wang
2023	J	`jnl`	Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. IEEE Trans. Signal Process. Siyuan Lu, Chenchen Zhou, Keli Xie, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design. ACM Trans. Design Autom. Electr. Syst. Lang Feng, Wenjian Liu, Chuliang Guo, Ke Tang, Cheng Zhuo, Zhongfeng Wang
2023	—	`conf`	High-Throughput Hardware Implementation for Haraka in SPHINCS+. ISQED Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang
2023	J	`jnl`	Intelligent Typography: Artistic Text Style Transfer for Complex Texture and Structure. IEEE Trans. Multim. Wendong Mao, Shuai Yang, Huihong Shi, Jiaying Liu, Zhongfeng Wang
2023	J	`jnl`	Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation. IACR Trans. Cryptogr. Hardw. Embed. Syst. Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang
2023	J	`jnl`	Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IEEE Trans. Computers Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
2023	J	`jnl`	NASA+: Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Huihong Shi, Haoran You, Zhongfeng Wang, Yingyan Lin
2023	C	`conf`	PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. ISCAS Qiong Li, Chao Fang, Zhongfeng Wang
2023	J	`jnl`	PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. CoRR Qiong Li, Chao Fang, Zhongfeng Wang
2023	J	`jnl`	PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender. CoRR Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang
2023	J	`jnl`	ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xinrui Wang, Lang Feng, Zhongfeng Wang
2023	J	`jnl`	ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs Xiao Wu, Shuang Liang, Meiqi Wang, Zhongfeng Wang
2023	J	`jnl`	Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang
2023	J	`jnl`	Rethinking Parallel Memory Access Pattern in Number Theoretic Transform Design. IEEE Trans. Circuits Syst. II Express Briefs Yue Geng, Xiao Hu, Minghao Li, Zhongfeng Wang
2023	—	`conf`	S$$^2$$R: Exploring a Double-Win Transformer-Based Framework for Ideal and Blind Super-Resolution. ICANN (6) Minghao She, Wendong Mao, Huihong Shi, Zhongfeng Wang
2023	J	`jnl`	S2R: Exploring a Double-Win Transformer-Based Framework for Ideal and Blind Super-Resolution. CoRR Minghao She, Wendong Mao, Huihong Shi, Zhongfeng Wang
2023	A*	`conf`	ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention. HPCA Jyotikrishna Dass, Shang Wu, Huihong Shi, Chaojian Li, Zhifan Ye, Zhongfeng Wang, Yingyan Lin
2022	J	`jnl`	A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. Xiao Wu, Yufei Ma, Meiqi Wang, Zhongfeng Wang
2022	C	`conf`	A High-Speed Codec Architecture for Lagrange Coded Computing. ISCAS Bohang Xiong, Jing Tian, Zhongfeng Wang
2022	—	`conf`	A Modified BP Bit-Flipping Algorithm for Polar Codes. SiPS Lijuan Li, Hangxuan Cui, Yangcan Zhou, Zhongfeng Wang
2022	C	`conf`	A Novel Interleaving Scheme for Concatenated Codes on Burst-Error Channel. APCC Lu Liu, Suwen Song, Zhongfeng Wang
2022	C	`conf`	A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm. ISCAS Peixiang Yang, Wendong Mao, Zhongfeng Wang, Jun Lin
2022	J	`jnl`	A Reliability Profile Based Low-Complexity Dynamic Schedule LDPC Decoding. IEEE Access Ruijia Yuan, Tianjiao Xie, Zhongfeng Wang
2022	J	`jnl`	A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. Suwen Song, Hangxuan Cui, Zhongfeng Wang
2022	J	`jnl`	A low latency traffic sign detection model with an automatic data labeling pipeline. Neural Comput. Appl. Jiapeng Luo, Zhongfeng Wang
2022	C	`conf`	Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm. ISCAS Ziqi Su, Wendong Mao, Zhongfeng Wang, Jun Lin, Wenqiang Wang, Haitao Sun
2022	—	`conf`	Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method. ISVLSI Binjing Li, Siyuan Lu, Keli Xie, Zhongfeng Wang
2022	J	`jnl`	An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. CoRR Chao Fang, Aojun Zhou, Zhongfeng Wang
2022	J	`jnl`	An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. IEEE Trans. Very Large Scale Integr. Syst. Chao Fang, Aojun Zhou, Zhongfeng Wang
2022	J	`jnl`	An Area-Efficient Message Passing Detector for Massive MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Suwen Song, Zhongfeng Wang
2022	—	`conf`	An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-Resolution. ISVLSI Siyu Zhang, Wendong Mao, Zhongfeng Wang
2022	—	`conf`	An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. AICAS Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Lin
2022	—	`conf`	An Efficient FPGA Accelerator for Point Cloud. SOCC Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin
2022	J	`jnl`	An Efficient FPGA Accelerator for Point Cloud. CoRR Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin
2022	C	`conf`	An Efficient FPGA-based Accelerator for Deep Forest. ISCAS Mingyu Zhu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang
2022	J	`jnl`	An Efficient FPGA-based Accelerator for Deep Forest. CoRR Mingyu Zhu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang
2022	C	`conf`	An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. ISCAS Chao Fang, Shouliang Guo, Wei Wu, Jun Lin, Zhongfeng Wang, Ming Kai Hsu, Lingzhi Liu
2022	C	`conf`	An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity. ISCAS Jian Huang, Jinming Lu, Zhongfeng Wang
2022	J	`jnl`	An Efficient High-Throughput Structured-Light Depth Engine. IEEE Trans. Very Large Scale Integr. Syst. Yichuan Bai, Mingzhe Jiang, Qingyu Zhu, Xiaoliang Chen, Yuan Du, Li Du, Zhongfeng Wang
2022	J	`jnl`	An Efficient Reconfigurable Encoder for the IEEE 1901 Standard. IEEE Trans. Very Large Scale Integr. Syst. Yuxing Chen, Hangxuan Cui, Zhongfeng Wang
2022	—	`conf`	An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. ISVLSI Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren
2022	J	`jnl`	Automatically search an optimal face detector for a specific deployment environment. EURASIP J. Adv. Signal Process. Jiapeng Luo, Zhongfeng Wang
2022	J	`jnl`	BEBERT: Efficient and robust binary ensemble BERT. CoRR Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang
2022	—	`conf`	Boosting Both Robustness and Hardware Efficiency via Random Pruning Mask Selection. ICANN (1) Ruixin Xue, Meiqi Wang, Zhongfeng Wang
2022	C	`conf`	Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting. ISCAS Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang
2022	J	`jnl`	Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. IEEE Trans. Very Large Scale Integr. Syst. Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
2022	J	`jnl`	Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2022	J	`jnl`	FACCU: Enable Fast Accumulation for High-Speed DSP Systems. IEEE Trans. Circuits Syst. II Express Briefs Meiqi Wang, Xin Cheng, Dingyang Zou, Zhongfeng Wang
2022	—	`conf`	FPGA-Accelerated Maze Routing Kernel for VLSI Designs. ASP-DAC Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang
2022	J	`jnl`	Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. CoRR Siyuan Lu, Chenchen Zhou, Keli Xie, Shiyi Liu, Jun Lin, Zhongfeng Wang
2022	—	`conf`	Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1). WCSP Ziyang Jiang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2022	J	`jnl`	GANDSE: Generative Adversarial Network based Design Space Exploration for Neural Network Accelerator Design. CoRR Lang Feng, Wenjian Liu, Chuliang Guo, Ke Tang, Cheng Zhuo, Zhongfeng Wang
2022	—	`conf`	High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. APCCAS Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang
2022	J	`jnl`	High-Throughput LDPC-CC Decoders Based on Storage, Arithmetic, and Control Improvements. IEEE Trans. Circuits Syst. II Express Briefs Yuxing Chen, Hangxuan Cui, Zhongfeng Wang
2022	J	`jnl`	Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiyuan Chen, Yufei Ma, Zhongfeng Wang
2022	J	`jnl`	Iterative Hard Thresholding Algorithm-Based Detector for Compressed OFDM-IM Systems. IEEE Commun. Lett. Baoling Hong, Hui Qian, Zhongfeng Wang
2022	J	`jnl`	LDPC decoding with locally informed dynamic scheduling based on the law of large numbers. IET Commun. Shuo Liang, Suipeng Xie, Xingcheng Liu, Zhongfeng Wang
2022	—	`conf`	Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC Codes. APCCAS Qinyuan Zhang, Suwen Song, Zhongfeng Wang
2022	—	`conf`	Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT. APCCAS Xinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang
2022	J	`jnl`	Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IACR Cryptol. ePrint Arch. Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
2022	Misc	`conf`	Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware. ICMLC Xin Cheng, Meiqi Wang, Yubo Shi, Jun Lin, Zhongfeng Wang
2022	J	`jnl`	Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression. IEEE Trans. Circuits Syst. I Regul. Pap. Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang
2022	A	`conf`	NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks. ICCAD Huihong Shi, Haoran You, Yang Zhao, Zhongfeng Wang, Yingyan Lin
2022	J	`jnl`	NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks. CoRR Huihong Shi, Haoran You, Yang Zhao, Zhongfeng Wang, Yingyan Lin
2022	A	`conf`	PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender. DATE Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang
2022	C	`conf`	Performance Analysis of Extended Integrated Interleaved Codes. APCC Keyue Deng, Xinyuan Qiao, Yuxing Chen, Suwen Song, Zhongfeng Wang
2022	C	`conf`	Reduction-Free Multiplication for Finite Fields and Polynomial Rings. WAIFI Samira Carolina Oliva Madrigal, Gökay Saldamli, Chen Li, Yue Geng, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
2022	J	`jnl`	Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness. IEEE Trans. Neural Networks Learn. Syst. Meiqi Wang, Liulu He, Jun Lin, Zhongfeng Wang
2022	J	`jnl`	RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity. IEEE Trans. Computers Lang Feng, Jiayi Huang, Luyi Li, Haochen Zhang, Zhongfeng Wang
2022	J	`jnl`	THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration. IEEE Trans. Very Large Scale Integr. Syst. Jinming Lu, Jian Huang, Zhongfeng Wang
2022	C	`conf`	UCViT: Hardware-Friendly Vision Transformer via Unified Compression. ISCAS Hongrui Song, Ya Wang, Meiqi Wang, Zhongfeng Wang
2022	J	`jnl`	ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention. CoRR Jyotikrishna Dass, Shang Wu, Huihong Shi, Chaojian Li, Zhifan Ye, Zhongfeng Wang, Yingyan Lin
2022	B	`conf`	View Dialogue in 2D: A Two-stream Model in Time-speaker Perspective for Dialogue Summarization and beyond. COLING Keli Xie, Dongchen He, Jiaxin Zhuang, Siyuan Lu, Zhongfeng Wang
2021	C	`conf`	A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference. ISCAS Kai Chen, Yimin Huang, Yuan Du, Zhuang Shao, Xingyu Gu, Li Du, Zhongfeng Wang
2021	J	`jnl`	A High-Speed Architecture for the Reduction in VDF Based on a Class Group. IACR Cryptol. ePrint Arch. Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
2021	—	`conf`	A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks. SiPS Yue Yu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang
2021	—	`conf`	A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA. ISVLSI Tongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang
2021	—	`conf`	A Stage-wise Conversion Strategy for Low-Latency Deformable Spiking CNN. SiPS Chunyu Wang, Jiapeng Luo, Zhongfeng Wang
2021	C	`conf`	Accelerating 3D Convolutional Neural Networks Using 3D Fast Fourier Transform. ISCAS Chao Fang, Liulu He, Haonan Wang, Jinghe Wei, Zhongfeng Wang
2021	J	`jnl`	An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoru Xie, Jun Lin, Zhongfeng Wang, Jinghe Wei
2021	—	`conf`	An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. ISVLSI Haikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	An Improved Method for Performance Analysis of Generalized Integrated Interleaved Codes. IEEE Commun. Lett. Hangxuan Cui, Suwen Song, Zhongfeng Wang
2021	J	`jnl`	An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2021	—	`conf`	Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks. SiPS Shize Zhao, Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter. J. Signal Process. Syst. Muhan Zheng, Yuanyong Luo, Hongbing Pan, Zhongfeng Wang, Yuan Xue
2021	—	`conf`	Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. ISVLSI Keyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang
2021	—	`conf`	DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. ASAP Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
2021	J	`jnl`	Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang
2021	Misc	`conf`	Elbert: Fast Albert with Confidence-Window Based Early Exit. ICASSP Keli Xie, Siyuan Lu, Meiqi Wang, Zhongfeng Wang
2021	J	`jnl`	Elbert: Fast Albert with Confidence-Window Based Early Exit. CoRR Keli Xie, Siyuan Lu, Meiqi Wang, Zhongfeng Wang
2021	J	`jnl`	Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers Jinming Lu, Chao Fang, Mingyang Xu, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. Jing Tian, Jun Lin, Zhongfeng Wang
2021	—	`conf`	Federated Regularization Learning: an Accurate and Safe Method for Federated Learning. AICAS Tianqi Su, Meiqi Wang, Zhongfeng Wang
2021	—	`conf`	Flexible-width Bit-level Compressor for Convolutional Neural Network. AICAS Junhan Zhu, Xiaoliang Chen, Li Du, Haoran Geng, Yichuan Bai, Yuandong Li, Yuan Du, Zhongfeng Wang
2021	J	`jnl`	Generalized Analog-to-Information Converter With Analysis Sparse Prior. IEEE Trans. Circuits Syst. I Regul. Pap. Hui Qian, Xinxin Song, Dengji Li, Zhongfeng Wang
2021	J	`jnl`	High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. Jing Tian, Bo Wu, Zhongfeng Wang
2021	C	`conf`	High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. ISCAS Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang
2021	B	`conf`	LITNet: A Light-weight Image Transform Net for Image Style Transfer. IJCNN Huihong Shi, Wendong Mao, Zhongfeng Wang
2021	—	`conf`	LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator. ISOCC Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang
2021	C	`conf`	Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. ISCAS Danyang Zhu, Jing Tian, Zhongfeng Wang
2021	J	`jnl`	Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading. IEEE Trans. Circuits Syst. I Regul. Pap. Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Low-complexity sphere decoding for MIMO-SCMA systems. IET Commun. Zhipeng Pan, Jing Lei, Lei Wen, Chaojing Tang, Zhongfeng Wang
2021	J	`jnl`	Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression. CoRR Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang
2021	—	`conf`	PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. ISVLSI Luyi Li, Jun Lin, Zhongfeng Wang
2021	C	`conf`	Transform-Based Feature Map Compression for CNN Inference. ISCAS Yubo Shi, Meiqi Wang, Siyi Chen, Jinghe Wei, Zhongfeng Wang
2020	—	`conf`	A Computation-Efficient Solution for Acceleration of Generative Adversarial Network. NEWCAS Peixiang Yang, Wendong Mao, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. SoCC Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A High-Speed Architecture for the Reduction in VDF Based on a Class Group. SoCC Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
2020	J	`jnl`	A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function. IEEE Trans. Circuits Syst. Zidi Qin, Yuou Qiu, Huaqing Sun, Zhonghai Lu, Zhongfeng Wang, Qinghong Shen, Hongbing Pan
2020	J	`jnl`	A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. ISVLSI Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang
2020	J	`jnl`	A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. Wenjian Liu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Reconfigurable DNN Training Accelerator on FPGA. SiPS Jinming Lu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security. SoCC Yuchen Mei, Li Du, Xuewen He, Yuan Du, Xiaoliang Chen, Zhongfeng Wang
2020	—	`conf`	A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems. NEWCAS Jing Zeng, Jun Lin, Zhongfeng Wang
2020	C	`conf`	A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm. ISCAS Yujie Zhang, Jiajun Wu, Minghao Li, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing. IEEE Access Zidi Qin, Yuou Qiu, Muhan Zheng, Hongxi Dong, Zhonghai Lu, Zhongfeng Wang, Hongbing Pan
2020	J	`jnl`	A lightweight face detector by integrating the convolutional neural network with the image pyramid. Pattern Recognit. Lett. Jiapeng Luo, Jiaying Liu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. APCCAS Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu
2020	—	`conf`	An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference. APCCAS Jiayu Wen, Yufei Ma, Zhongfeng Wang
2020	—	`conf`	An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse Converter. ISVLSI Chenhui Feng, Hui Qian, Zhongfeng Wang
2020	C	`conf`	An Optimized Compression Strategy for Compressor-Based Approximate Multiplier. ISCAS Manzhen Wang, Yuanyong Luo, Mengyu An, Yuou Qiu, Muhan Zheng, Zhongfeng Wang, Hongbing Pan
2020	J	`jnl`	Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data. IEICE Electron. Express Yongsheng Yin, Kangkang Sun, Hongmei Chen, Xiaolei Wang, Lu Liu, Honghui Deng, Xu Meng, Kun Li, Zhongfeng Wang
2020	—	`conf`	Efficient FPGA design for Convolutions in CNN based on FFT-pruning. APCCAS Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA. ISVLSI Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang
2020	—	`conf`	Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA. SoCC Xiao Wu, Yufei Ma, Zhongfeng Wang
2020	J	`jnl`	Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning. IEEE Trans. Circuits Syst. Danyang Zhu, Siyuan Lu, Meiqi Wang, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Exploring Quantization in Few-Shot Learning. NEWCAS Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Wendong Mao, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. APCCAS Xiao Hu, Jing Tian, Zhongfeng Wang
2020	J	`jnl`	Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2020	—	`conf`	Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model. SiPS Binjing Li, Fenggui Liu, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Fine-Grained Bit-Flipping Decoding for LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Yuxing Chen, Hangxuan Cui, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. IEEE Trans. Very Large Scale Integr. Syst. Yuxuan Wang, Yuanyong Luo, Zhongfeng Wang, Qinghong Shen, Hongbing Pan
2020	C	`conf`	Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading. ISCAS Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. SoCC Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. CoRR Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier. IACR Cryptol. ePrint Arch. Jing Tian, Bo Wu, Zhongfeng Wang
2020	—	`conf`	In-Memory Computing: The Next-Generation AI Computing Paradigm. ACM Great Lakes Symposium on VLSI Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Information Storage Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Hangxuan Cui, Jun Lin, Zhongfeng Wang
2020	—	`conf`	LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. APCCAS Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang
2020	B	`conf`	LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion. IJCNN Binjing Li, Keli Xie, Siyuan Lu, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Multi-Layer Generalized Integrated Interleaved Codes. IEEE Commun. Lett. Wenjie Li, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2020	A	`conf`	Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks. ICCAD Zhiyuan Chen, Yufei Ma, Zhongfeng Wang
2020	—	`conf`	Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task. SiPS Haonan Wang, Yuchen Mei, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Jing Tian, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Wenjie Li, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. IEEE Access Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. CoRR Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs Yangcan Zhou, Zhiyu Chen, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes. SiPS Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. ISVLSI Zengchao Yan, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. SiPS Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, Li Du
2019	Misc	`conf`	A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks. ICASSP Haonan Wang, Wenjian Liu, Tianyi Xu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. IEEE Trans. Circuits Syst. II Express Briefs Congyi Zhu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A New Fast-SSC-Flip Decoding of Polar Codes. ICC Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A New Inversionless Berlekamp-Massey Algorithm with Efficient Architecture. SiPS Chao Chen, Yunghsiang S. Han, Zhongfeng Wang, Baoming Bai
2019	C	`conf`	A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes. ISCAS Hangxuan Cui, Jun Lin, Suwen Song, Zhongfeng Wang
2019	C	`conf`	A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs. IEICE Electron. Express Yongsheng Yin, Liu Liu, Hongmei Chen, Honghui Deng, Xu Meng, Jing-Sheng Wu, Zhongfeng Wang
2019	J	`jnl`	An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Hangxuan Cui, Jun Lin, Zhongfeng Wang
2019	C	`conf`	An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Hangxuan Cui, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li
2019	J	`jnl`	Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs Congyi Zhu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter. SiPS Yuanyong Luo, Hongbing Pan, Qinghong Shen, Zhongfeng Wang
2019	J	`jnl`	Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". IEEE Trans. Very Large Scale Integr. Syst. Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
2019	J	`jnl`	Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm. CoRR Haonan Wang, Jun Lin, Zhongfeng Wang
2019	—	`conf`	DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks. SiPS Meiqi Wang, Jianqiao Mo, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. Meiqi Wang, Zhisheng Wang, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing. SiPS Wenjian Liu, Xiayuan Wen, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Yizhi Wang, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. ISVLSI Xiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. IEEE Trans. Very Large Scale Integr. Syst. Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
2019	—	`conf`	Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. ISVLSI Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li
2019	—	`conf`	Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems. SiPS Jing Zeng, Jun Lin, Zhongfeng Wang, Yun Chen
2019	J	`jnl`	Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes. IEEE Access Xingcheng Liu, Li'e Zi, Dong Yang, Zhongfeng Wang
2019	J	`jnl`	Improved Fast-SSC-Flip Decoding of Polar Codes. IEEE Commun. Lett. Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	C	`conf`	Methodology for Efficient Reconfigurable Architecture of Generative Neural Network. ISCAS Wendong Mao, Jichen Wang, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019	A*	`conf`	TIE: energy-efficient tensor train-based inference engine for deep neural network. ISCA Chunhua Deng, Fangxuan Sun, Xuehai Qian, Jun Lin, Zhongfeng Wang, Bo Yuan
2019	—	`conf`	Training Deep Neural Networks Using Posit Number System. SoCC Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	Training Deep Neural Networks Using Posit Number System. CoRR Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du
2019	C	`conf`	USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network. ISCAS Wenjian Liu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS Jing Tian, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs Jing Tian, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning. APCCAS Meiqi Wang, Siyuan Lu, Danyang Zhu, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A High-Throughout Real-Time Prewitt Operator on Embedded NEON+ARM System. APCCAS Chenxi Lin, Hui Qian, Zhongfeng Wang
2018	C	`conf`	A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. ISCAS Yaqi Wang, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A Novel Compiler for Regular Expression Matching Engine Construction. APCCAS Xin Jin, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	A Stage-Combined Belief Propagation Decoder for Polar Codes. J. Signal Process. Syst. Jin Sha, Jingbo Liu, Jun Lin, Zhongfeng Wang
2018	C	`conf`	An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. ISCAS Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	C	`conf`	An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS Jing Tian, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs Jing Zeng, Jun Lin, Zhongfeng Wang
2018	—	`conf`	An Optimized Architecture For Decomposed Convolutional Neural Networks. ISVLSI Fangxuan Sun, Jun Lin, Zhongfeng Wang
2018	—	`conf`	Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS Jing Tian, Jun Lin, Zhongfeng Wang
2018	—	`conf`	Approximate Comparator: Design and Analysis. SiPS Yangcan Zhou, Jun Lin, Jichen Wang, Zhongfeng Wang
2018	—	`conf`	Bandwidth Efficient Architectures for Convolutional Neural Network. SiPS Jichen Wang, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	CORDIC-Based Architecture for Computing Nth Root and Its Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. Yuanyong Luo, Yuxuan Wang, Huaqing Sun, Yi Zha, Zhongfeng Wang, Hongbing Pan
2018	J	`jnl`	Design of Binary LDPC Codes With Parallel Vector Message Passing. IEEE Trans. Commun. Xingcheng Liu, Feng Xiong, Zhongfeng Wang, Shuo Liang
2018	Misc	`conf`	Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks. ICASSP Fangxuan Sun, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Efficient Hardware Architectures for Deep Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Jichen Wang, Jun Lin, Zhongfeng Wang
2018	Misc	`conf`	Efficient Reconfigurable Hardware Core for Convolutional Neural Networks. ACSSC Haonan Wang, Jun Lin, Yi Xie, Bo Yuan, Zhongfeng Wang
2018	—	`conf`	FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. ISVLSI Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	—	`conf`	Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes. APCCAS Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference. IEEE Signal Process. Lett. Zhisheng Wang, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems. IEEE Wirel. Commun. Lett. Jing Zeng, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	SGAD: Soft-Guided Adaptively-Dropped Neural Network. CoRR Zhisheng Wang, Fangxuan Sun, Jun Lin, Zhongfeng Wang, Bo Yuan
2018	J	`jnl`	Stuck-at-close defect propagation and its blocking technique in CMOL cell mapping. Microelectron. J. Dingheng Chen, Yinshui Xia, Zhongfeng Wang
2017	J	`jnl`	Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. IEEE Trans. Very Large Scale Integr. Syst. Zhisheng Wang, Jun Lin, Zhongfeng Wang
2017	J	`jnl`	Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. Chuan Zhang, Yuan-Hao Huang, Farhana Sheikh, Zhongfeng Wang
2017	C	`conf`	Algorithm and architecture for joint detection and decoding for MIMO with LDPC codes. ISCAS Shusen Jing, Junmei Yang, Zhongfeng Wang, Xiaohu You, Chuan Zhang
2017	J	`jnl`	Analysis and Comparison of FEC Schemes for 200GbE and 400GbE. IEEE Commun. Stand. Mag. Tongtong Wang, Zhongfeng Wang, Xinyuan Wang, Junqing Sun, Ali Ghiasi
2017	J	`jnl`	Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos
2017	J	`jnl`	Dynamical Textures Modeling via Joint Video Dictionary Learning. IEEE Trans. Image Process. Xian Wei, Yuanxiang Li, Hao Shen, Fang Chen, Martin Kleinsteuber, Zhongfeng Wang
2017	J	`jnl`	Efficient Soft Cancelation Decoder Architectures for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Zhiyuan Yan, Zhongfeng Wang
2017	C	`conf`	Efficient approximate layered LDPC decoder. ISCAS Yangcan Zhou, Jun Lin, Zhongfeng Wang
2017	—	`conf`	Efficient fast convolution architectures for convolutional neural network. ASICON Weihong Xu, Zhongfeng Wang, Xiaohu You, Chuan Zhang
2017	—	`conf`	Energy efficient SVM classifier using approximate computing. ASICON Yangcan Zhou, Jun Lin, Zhongfeng Wang
2017	J	`jnl`	Fully-Parallel Area-Efficient Deep Neural Network Design Using Stochastic Computing. IEEE Trans. Circuits Syst. II Express Briefs Yi Xie, Siyu Liao, Bo Yuan, Yanzhi Wang, Zhongfeng Wang
2017	J	`jnl`	Guest Editorial Advanced Baseband Processing Circuits and Systems for 5G Communications. IEEE J. Emerg. Sel. Topics Circuits Syst. Chuan Zhang, Yuan-Hao Huang, Farhana Sheikh, Zhongfeng Wang
2017	J	`jnl`	High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. IEEE Trans. Very Large Scale Integr. Syst. Guanghui Hu, Jin Sha, Zhongfeng Wang
2017	—	`conf`	Low-complexity detection algorithms based on matrix partition for massive MIMO. WCSP Haijian Wu, Jun Lin, Chuan Zhang, Zhongfeng Wang
2017	—	`conf`	Reduced complexity message passing detection algorithm in large-scale MIMO systems. WCSP Haochuan Zhu, Jun Lin, Zhongfeng Wang
2017	Misc	`conf`	Segmented successive cancellation list polar decoding with joint BCH-CRC codes. ACSSC Xiao Liang, Huayi Zhou, Zhongfeng Wang, Xiaohu You, Chuan Zhang
2016	C	`conf`	A high throughput belief propagation decoder architecture for polar codes. ISCAS Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang
2016	J	`jnl`	An Efficient FPGA Implementation for 2-D MUSIC Algorithm. Circuits Syst. Signal Process. Kai Huang, Jin Sha, Wei Shi, Zhongfeng Wang
2016	—	`conf`	An Efficient Hardware Architecture for Lossless Data Compression in Data Center. SiPS Zhisheng Wang, Jun Lin, Zhongfeng Wang
2016	—	`conf`	Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing. ACM Great Lakes Symposium on VLSI Bo Yuan, Yanzhi Wang, Zhongfeng Wang
2016	J	`jnl`	Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing. IEEE Trans. Circuits Syst. II Express Briefs Bo Yuan, Yanzhi Wang, Zhongfeng Wang
2016	C	`conf`	Area-efficient scaling-free DFT/FFT design using stochastic computing. ISCAS Bo Yuan, Yanzhi Wang, Zhongfeng Wang
2016	—	`conf`	Beyond 100Gbps Encoder Design for Staircase Codes. SiPS Guanghui Hu, Jin Sha, Zhongfeng Wang
2016	—	`conf`	Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization. SiPS Jun Zhou, Zhongfeng Wang, Sebastian Hoyos
2016	Misc	`conf`	Design space exploration for hardware-efficient stochastic computing: A case study on discrete cosine transformation. ICASSP Bo Yuan, Chuan Zhang, Zhongfeng Wang
2016	—	`conf`	Efficient convolution architectures for convolutional neural network. WCSP Jichen Wang, Jun Lin, Zhongfeng Wang
2016	—	`conf`	Intra-layer nonuniform quantization of convolutional neural network. WCSP Fangxuan Sun, Jun Lin, Zhongfeng Wang
2016	C	`conf`	Stage-combined belief propagation decoding of polar codes. ISCAS Jin Sha, Jun Lin, Zhongfeng Wang
2015	—	`conf`	A stage-reduced low-latency successive cancellation decoder for polar codes. DSP Xing Liu, Jin Sha, Chuan Zhang, Zhongfeng Wang
2014	—	`conf`	Area-efficient check node unit architecture for single block-row quasi-cyclic LDPC codes. APCCAS Chuan Zhang, Shenghui Weng, Xiaohu You, Zhongfeng Wang
2014	J	`jnl`	Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Chuan Zhang, Zhongfeng Wang, Xiaohu You
2014	Misc	`conf`	Efficient adaptive list successive cancellation decoder for polar codes. ACSSC Chuan Zhang, Zhongfeng Wang, Xiaohu You, Bo Yuan
2014	C	`conf`	Efficient column-layered decoders for single block-row quasi-cyclic LDPC codes. ISCAS Chuan Zhang, Xiaohu You, Zhongfeng Wang
2014	C	`conf`	Efficient symbol reliability based decoding for QCNB-LDPC codes. ISCAS Leixin Zhou, Jin Sha, Yun Chen, Chuan Zhang, Zhongfeng Wang
2014	C	`conf`	Multilevel error correction scheme for MLC flash memory. ISCAS Zhiqiang Cui, Zhongfeng Wang, Xinming Huang
2013	C	`conf`	Memory efficient EMS decoding for non-binary LDPC codes. ISCAS Leixin Zhou, Jin Sha, Yun Chen, Zhongfeng Wang
2012	J	`jnl`	A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network. IEEE Trans. Circuits Syst. II Express Briefs Xinmiao Zhang, Zhongfeng Wang
2012	—	`conf`	Efficient EMS decoding for non-binary LDPC codes. ISOCC Leixin Zhou, Jin Sha, Zhongfeng Wang
2012	J	`jnl`	High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. IEEE Trans. Very Large Scale Integr. Syst. Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, Kai Zhang
2012	C	`conf`	Memory efficient column-layered decoder design for non-binary LDPC codes. ISCAS Kai He, Jin Sha, Zhongfeng Wang
2012	J	`jnl`	Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing. IEEE Trans. Circuits Syst. II Express Briefs Kai He, Jin Sha, Zhongfeng Wang
2012	J	`jnl`	Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes CoRR Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
2012	J	`jnl`	Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. Li Li, Bo Yuan, Zhongfeng Wang, Jin Sha, Hongbing Pan, Weishan Zheng
2011	J	`jnl`	A High-Throughput LDPC Decoder Architecture With Rate Compatibility. IEEE Trans. Circuits Syst. I Regul. Pap. Kai Zhang, Xinming Huang, Zhongfeng Wang
2011	—	`conf`	Memory efficient decoder design of nonbinary LDPC codes. ISOCC Kai He, Jin Sha, Zhongfeng Wang
2011	J	`jnl`	Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
2010	J	`jnl`	A dual-rate LDPC decoder for china multimedia mobile broadcasting systems. IEEE Trans. Consumer Electron. Kai Zhang, Xinming Huang, Zhongfeng Wang
2010	J	`jnl`	An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010	J	`jnl`	Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010	J	`jnl`	Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin
2010	C	`conf`	Layered decoding for non-binary LDPC codes. ISCAS Shuai Zhou, Jin Sha, Li Li, Zhongfeng Wang
2010	C	`conf`	Low power decoder design for QC-LDPC codes. ISCAS Kai He, Jin Sha, Li Li, Zhongfeng Wang
2010	C	`conf`	Memory-reduced MAP decoding for double-binary convolutional Turbo code. ISCAS Jinjin He, Zhongfeng Wang, Huaping Liu
2009	—	`conf`	An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems. ASAP Kai Zhang, Xinming Huang, Zhongfeng Wang
2009	—	`conf`	An improved min-sum based column-layered decoding algorithm for LDPC codes. SiPS Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2009	J	`jnl`	An improved scaled DCT architecture. IEEE Trans. Consumer Electron. Zhigang Wu, Jin Sha, Zhongfeng Wang, Li Li, Minglun Gao
2009	C	`conf`	Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications. ISCAS Bo Yuan, Li Li, Jin Sha, Zhongfeng Wang
2009	J	`jnl`	Area-efficient reed-solomon decoder design for optical communications. IEEE Trans. Circuits Syst. II Express Briefs Bo Yuan, Zhongfeng Wang, Li Li, Minglun Gao, Jin Sha, Chuan Zhang
2009	J	`jnl`	Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang
2009	J	`jnl`	Decoder Design for RS-Based LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2009	J	`jnl`	Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao
2009	J	`jnl`	High-Throughput Layered LDPC Decoding Architecture. IEEE Trans. Very Large Scale Integr. Syst. Zhiqiang Cui, Zhongfeng Wang, Youjian Liu
2009	—	`conf`	High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. SiPS Bo Yuan, Li Li, Zhongfeng Wang
2009	C	`conf`	High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications. ISCAS Chuan Zhang, Li Li, Jun Xu, Zhongfeng Wang
2009	J	`jnl`	High-throughput layered decoder implementation for quasi-cyclic LDPC codes. IEEE J. Sel. Areas Commun. Kai Zhang, Xinming Huang, Zhongfeng Wang
2009	C	`conf`	LDPC Decoder Design for IEEE 802.15 Standard. ISCAS Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang
2009	J	`jnl`	LDPC decoder design for high rate wireless personal area networks. IEEE Trans. Consumer Electron. Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2009	J	`jnl`	Multi-Gb/s LDPC Code Design and Implementation. IEEE Trans. Very Large Scale Integr. Syst. Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li
2009	C	`conf`	Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li
2008	C	`conf`	A low-complexity high-performance noncoherent receiver for GFSK signals. ISCAS Jinjin He, Jian Cui, Lianxing Yang, Zhongfeng Wang
2008	C	`conf`	Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. ICCD Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang
2008	—	`conf`	Efficient architecture for the Tate pairing in characteristic three. APCCAS Qingwei Li, Zhongfeng Wang, Xinmiao Zhang, Xingcheng Liu
2008	—	`conf`	Efficient decoder design for high-throughput LDPC decoding. APCCAS Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia
2008	—	`conf`	Efficient radius and list updating units design for list sphere decoders. APCCAS Qingwei Li, Zhongfeng Wang, Xingcheng Liu
2008	—	`conf`	Error correction for multi-level NAND flash memory using Reed-Solomon codes. SiPS Bainan Chen, Xinmiao Zhang, Zhongfeng Wang
2008	—	`conf`	Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI Zhiqiang Cui, Zhongfeng Wang
2008	—	`conf`	Fast point operation architecture for Elliptic Curve Cryptography. APCCAS Qingwei Li, Zhongfeng Wang, Xingcheng Liu
2008	J	`jnl`	Improved low-complexity low-density parity-check decoding. IET Commun. Zhiqiang Cui, Zhongfeng Wang
2008	—	`conf`	Low-complexity high-speed 4-D TCM decoder. SiPS Jinjin He, Zhongfeng Wang, Huaping Liu
2008	—	`conf`	Low-complexity shift-LDPC decoder for high-speed communication systems. APCCAS Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang
2008	C	`conf`	Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. ISCAS Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang
2007	J	`jnl`	A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Zhiqiang Cui
2007	—	`conf`	Design of Low-Power Memory-Efficient Viterbi Decoder. SiPS Lupin Chen, Jinjin He, Zhongfeng Wang
2007	C	`conf`	Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ISCAS Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen
2007	—	`conf`	Early-Pruning K-Best Sphere Decoder for MIMO Systems. SiPS Qingwei Li, Zhongfeng Wang
2007	C	`conf`	Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS Zhiqiang Cui, Zhongfeng Wang
2007	C	`conf`	FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. ISCAS Qinqin Chen, Zhongfeng Wang, Jun Ma
2007	—	`conf`	Factorization Architecture by Direct Root Computation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ICASSP (2) Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen
2007	—	`conf`	Fast EBCOT Encoder Architecture for JPEG 2000. SiPS Somya Rathi, Zhongfeng Wang
2007	J	`jnl`	High-Speed Recursion Architectures for MAP-Based Turbo Decoders. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang
2007	J	`jnl`	Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Zhiqiang Cui
2007	J	`jnl`	Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Ma, Alexander Vardy, Zhongfeng Wang
2007	—	`conf`	Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS Zhiqiang Cui, Zhongfeng Wang
2007	J	`jnl`	Very Low-Complexity Hardware Interleaver for Turbo Decoding. IEEE Trans. Circuits Syst. II Express Briefs Zhongfeng Wang, Qingwei Li
2006	C	`conf`	A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS Zhiqiang Cui, Zhongfeng Wang
2006	—	`conf`	An FPGA Implementation of Array LDPC Decoder. APCCAS Jin Sha, Minglun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang
2006	C	`conf`	Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS Zhiqiang Cui, Zhongfeng Wang
2006	C	`conf`	Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes. ISCAS Jun Ma, Alexander Vardy, Zhongfeng Wang
2006	J	`jnl`	High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Jun Ma
2006	C	`conf`	Improved k-best sphere decoding algorithms for MIMO systems. ISCAS Qingwei Li, Zhongfeng Wang
2006	C	`conf`	Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code. ISCAS Jun Ma, Alexander Vardy, Zhongfeng Wang
2006	—	`conf`	Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems. ICASSP (3) Zhongfeng Wang, Yuping Zhang, Keshab K. Parhi
2004	—	`conf`	Area efficient decoding of quasi-cyclic low density parity check codes. ICASSP (5) Zhongfeng Wang, Yanni Chen, Keshab K. Parhi
2004	J	`jnl`	On the better protection of short-frame turbo codes. IEEE Trans. Commun. Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi
2003	—	`conf`	Efficient interleaver memory architectures for serial turbo decoding. ICASSP (2) Zhongfeng Wang, Keshab K. Parhi
2003	J	`jnl`	High performance, high throughput turbo/SOVA decoder design. IEEE Trans. Commun. Zhongfeng Wang, Keshab K. Parhi
2002	J	`jnl`	Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi
2001	Misc	`conf`	A study on the performance, power consumption tradeoffs of short frame turbo decoder design. ICASSP Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi
2001	Misc	`conf`	Area-efficient high speed decoding schemes for turbo/MAP decoders. ICASSP Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi
2001	J	`jnl`	Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders. J. VLSI Signal Process. Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi
2001	—	`conf`	On finite precision implementation of low density parity check codes decoder. ISCAS (4) Tong Zhang, Zhongfeng Wang, Keshab K. Parhi
2000	—	`conf`	A K=3, 2 Mbps low power turbo decoder for 3 CICC Hiroshi Suzuki, Zhongfeng Wang, Keshab K. Parhi
2000	Misc	`conf`	Decoding metrics and their applications in VLSI turbo decoders. ICASSP Zhongfeng Wang, Keshab K. Parhi
2000	C	`conf`	Efficient approaches to improving performance of VLSI SOVA-based turbo decoders. ISCAS Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi
2000	Misc	`conf`	High throughput low energy FEC/ARQ technique for short frame turbo codes. ICASSP Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi
1999	—	`conf`	Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ISCAS (3) Stephen Summerfield, Zhongfeng Wang, Keshab K. Parhi