Zhiyi Yu

163 papers A* 4A 5B 4C 15Misc 2Journal 80Unranked 53
YearRankTypeTitle / Venue / Authors
2026 — conf
An Algorithm-Hardware Co-Design for Efficient and Robust Spiking Neural Networks via Sparsity.
ASP-DAC
Wei Liu, Yinsheng Chen, Jilong Luo, Yusa Wang, Zhiyi Yu, Shanlin Xiao
2026 A* conf
LRM-GPU: Alleviating Synchronization Overhead for Multi-Chiplet GPU Architecture.
HPCA
Baiqing Zhong, Zhirong Ye, Xiaojie Li, Peilin Wang, Haiqiu Huang, Zhaolin Li, Zhiyi Yu, Mingyu Wang
2026 — conf
NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems.
ASP-DAC
Zhirong Ye, Yongchang Zhang, Peilin Wang, Tao Lu, Zhaolin Li, Zhiyi Yu, Mingyu Wang
2026 J jnl
Robust High-Accuracy Cellular Base Station Positioning for User Equipment Based on Multi-Signal Fusion Passive Imaging.
IEEE Trans. Veh. Technol.
Yang Zhao, Zhiting Li, Baode Lin, Zechen Li, Zhiyi Yu, Weiwen Zou
2026 — conf
Spiking-NeRF: Neural Graphics Acceleration With Spiking Feature Encoding for Edge 3D Rendering.
ASP-DAC
Jianzhen Gao, Wei Liu, Yue Liu, Hengyi Zhou, Zhiyi Yu, Shanlin Xiao
2026 J jnl
SynapseHD: A unified training framework for bridging spiking neural networks and hyperdimensional computing.
Neurocomputing
Lingfeng Zhou, Huiyao Wang, Bohan Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2026 J jnl
UniCNet: Unified Cycle-Accurate Simulation for Composable Chiplet Network With Modular Design-Integration Workflow.
IEEE Comput. Archit. Lett.
Peilin Wang, Mingyu Wang, Zhirong Ye, Tao Lu, Zhiyi Yu
2025 — conf
A Half-Bit-Per-Cell Strategy for Enhancing Flash Memory Reliability in Harsh Environments.
IRPS
Ruibin Zhou, Yuhan Wang, Jian Huang, Zecheng Xu, Xianping Liu, Xinrui Zhang, Zhiyi Yu
2025 J jnl
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms.
IEEE Trans. Circuits Syst. II Express Briefs
Haiqiu Huang, Mingyu Wang, Xiaojie Li, Baiqing Zhong, Zeqi Yang, Tao Lu, Yicong Zhang, Zhiyi Yu
2025 J jnl
A Hybrid Stochastic-Binary Computing Batch Normalization Engine for Low-Power On-Chip Learning Spiking Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Liu, Yue Liu, Zhiyi Yu, Shanlin Xiao
2025 A conf
A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory.
DATE
Ruibin Zhou, Jian Huang, Xianping Liu, Yuhan Wang, Xinrui Zhang, Yungen Peng, Zhiyi Yu
2025 J jnl
A Low-Cost Secure Branch Predictor to Mitigate the Speculative Attacks by Disrupting Setup Phase.
IEEE Trans. Very Large Scale Integr. Syst.
Runye Ding, Yuyang Liu, Yujie Chen, Yao Liu, Zhiyi Yu
2025 — conf
A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits.
ISQED
Bohan Wang, Zeyang Xu, Lingfeng Zhou, Huiyao Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 J jnl
ADP-Net: a hierarchical attention-diffusion-prediction framework for human trajectory prediction.
Frontiers Artif. Intell.
Zhenggui Zhang, Shanlin Xiao, Zhiyi Yu
2025 J jnl
ASNA-Flow: An Efficient Asynchronous Neuromorphic Accelerator for Real-Time Event-Based Optical Flow.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu, Shanlin Xiao
2025 J jnl
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu
2025 A* conf
C3ache: Towards Hierarchical Cache-Centric Computing for Sparse Matrix Multiplication on GPGPUs.
MICRO
Xiaojie Li, Mingyu Wang, Baiqing Zhong, Haiqiu Huang, Guangjie Cao, Zhiyi Yu
2025 J jnl
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yao Qin, Mingyu Wang, Jiahua Yan, Tao Lu, Zhiyi Yu
2025 A conf
FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation.
DATE
Xiangyu Li, Weichong Chen, Ruida Hong, Jinghai Wang, Ningyuan Yin, Zhiyi Yu
2025 A conf
Faster-SNN: Towards Faster and Better Spiking Neural Networks with Hybrid Neural Coding.
ICME
Yinsheng Chen, Jilong Luo, Zhiyi Yu, Shanlin Xiao
2025 J jnl
Low-Power and Low-Cost AI Processor With Distributed-Aggregated Classification Architecture for Wearable Epilepsy Seizure Detection.
IEEE Trans. Biomed. Circuits Syst.
Qiang Zhang, Mingyue Cui, Yue Liu, Weichong Chen, Zhiyi Yu
2025 — conf
SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks.
ASP-DAC
Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao
2025 A conf
Stair-LIF: Boosting the Representation of Spiking Neural Networks with Learnable Incremental Multi-Threshold Neurons.
ICME
Jilong Luo, Yinsheng Chen, Yue Liu, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 A* conf
Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution.
DAC
Yihe Yu, Bo Li, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu, Shanlin Xiao
2025 J jnl
UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor.
Microelectron. J.
Qiang Zhang, Mingyue Cui, Weichong Chen, Yue Liu, Zhiyi Yu
2024 — conf
An Adaptive Re-Read Strategy for Mitigating Temporary Read Errors in 3D-NAND Flash Solid-State Drives.
NVMSA
Ruibin Zhou, Yuhan Wang, Jian Huang, Xinrui Zhang, Xianping Liu, Zhiyi Yu
2024 A conf
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint.
DATE
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 — conf
An FPGA-based QDI Asynchronous Circuits Design Methodology.
ICTA
Guangyao Lin, Jinghai Wang, Zeyang Xu, Zhiyi Yu, Shanlin Xiao
2024 A* conf
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations.
MICRO
Yicong Zhang, Mingyu Wang, Wangguang Wang, Yangzhan Mai, Haiqiu Huang, Zhiyi Yu
2024 — conf
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM.
ISVLSI
Xiaojie Li, Mingyu Wang, Yangzhan Mai, Yicong Zhang, Baiqing Zhong, Zhiyi Yu
2024 J jnl
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 C conf
CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation.
ICCD
Baiqing Zhong, Mingyu Wang, Yicong Zhang, Xiaojie Li, Zhiyi Yu
2024 J jnl
Contrastive learning for unsupervised sentence embeddings using negative samples with diminished semantics.
J. Supercomput.
Zhiyi Yu, Hong Li, Jialin Feng
2024 — conf
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s.
ISVLSI
Yukun Wei, Mingyu Wang, Haiqiu Huang, Wangguang Wang, Zhiyi Yu
2024 — conf
Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator.
ICTA
Bo Li, Wei Liu, Yue Liu, Xiao Huang, Zhiyi Yu, Shanlin Xiao
2024 J jnl
Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism.
J. Intell. Inf. Syst.
Jialin Feng, Hong Li, Zhiyi Yu
2024 J jnl
Enhancing text classification with attention matrices based on BERT.
Expert Syst. J. Knowl. Eng.
Zhiyi Yu, Hong Li, Jialin Feng
2024 J jnl
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift.
IEEE Trans. Circuits Syst. II Express Briefs
Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 J jnl
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style.
IEEE Trans. Circuits Syst. II Express Briefs
Wanyuan Pan, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu
2024 J jnl
SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule.
IEEE Trans. Biomed. Circuits Syst.
Wei Liu, Shanlin Xiao, Yue Liu, Zhiyi Yu
2024 Misc conf
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.
ICASSP
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
2024 J jnl
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2023 C conf
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips.
ISCAS
Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu
2023 J jnl
A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations.
IEICE Electron. Express
Xing Jin, Ningyuan Yin, Weichong Chen, Ximing Li, Guihua Zhao, Zhiyi Yu
2023 — conf
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference.
ISVLSI
Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu
2023 J jnl
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu
2023 J jnl
A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers.
IEICE Trans. Electron.
Xiangyu Meng, Yecong Li, Zhiyi Yu
2023 J jnl
A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS.
IEICE Trans. Electron.
Xiangyu Meng, Kangfeng Wei, Zhiyi Yu, Xinlun Cai
2023 B conf
A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems.
ICPADS
Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu
2023 — conf
CRAFT: Common Router Architecture for Throughput Optimization.
ICA3PP (3)
Jiahua Yan, Mingyu Wang, Yao Qin, Zhiyi Yu
2023 J jnl
Computing Resistance-Style Image Sensors for Artificial Neural Networks.
IEEE Internet Things J.
Guihua Zhao, Yating Peng, Yizhan Wang, Caihua Wan, Xianping Liu, Yu Zhang, Xiufeng Han, Weichong Chen, Zhiyi Yu
2023 J jnl
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks.
CoRR
Jilong Luo, Shanlin Xiao, Yinsheng Chen, Zhiyi Yu
2023 J jnl
High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Xing Jin, Weichong Chen, Ximing Li, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu
2023 B conf
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs.
ICPADS
Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu
2023 J jnl
Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation.
IEEE Trans. Circuits Syst. II Express Briefs
Ximing Li, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu
2023 J jnl
Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs.
Microelectron. J.
Yicong Zhang, Mingyu Wang, Wangguang Wang, Zhiyi Yu
2023 J jnl
SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.
CoRR
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
2023 J jnl
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs.
IEEE Trans. Very Large Scale Integr. Syst.
Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu
2023 — conf
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient.
ICTA
Kexin Huang, Wei Liu, Yue Liu, Shanlin Xiao, Zhiyi Yu
2023 — conf
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement.
ICTA
Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu
2022 — conf
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs.
ICTA
Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu
2022 J jnl
A dual-rail/single-rail hybrid system using null convention logic circuits.
Microelectron. J.
Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu
2022 J jnl
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu
2022 J jnl
An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks.
IEICE Electron. Express
Guihua Zhao, Xing Jin, Huafeng Ye, Yating Peng, Wei Liu, Ningyuan Yin, Weichong Chen, Jianjun Chen, Ximing Li, Zhiyi Yu
2022 — conf
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits.
ICTA
Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu
2022 — conf
Hardware Based RISC-V Instruction Set Randomization.
ICTA
Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu
2022 — conf
One Case of THOUGHT: Industry-University Converged Education Practice on Open Source.
ICCSE (3)
Zhiyi Yu, Chao Li, Chaochen Hu, Zhen Chen, Yandong Yao, Jiang Wu, Hao Wang, Jialun Du, Min Guo, Haoyu Wang, Weimin Li, Xiu Li, Xiaodong Ma, Yisong Zhang, Shuangshou Li
2021 Misc conf
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA.
FCCM
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
2021 J jnl
A Data-Driven Asynchronous Neural Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu
2021 J jnl
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method.
IEEE Trans. Circuits Syst. II Express Briefs
Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu
2021 — conf
A high throughput spatially coupled low density generator matrix coding system.
ICTA
Ziyuan Luo, Qingyi Xie, Shanlin Xiao, Zhiyi Yu
2021 J jnl
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ningyuan Yin, Baofa Huang, Xiaobai Chen, Jianjun Chen, Zhiyi Yu
2021 J jnl
Balancing the Cost and Performance Trade-Offs in SNN Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2021 J jnl
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks.
IEICE Electron. Express
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
2021 — conf
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs.
ICTA
Jian Wang, Huipeng Deng, Huafeng Ye, Shanlin Xiao, Zhiyi Yu
2021 J jnl
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing.
J. Electronic Imaging
Qiang Zhang, Shanlin Xiao, Zhiyi Yu, Huanliang Zheng, Peng Wang
2021 — conf
High-Throughput Zipper Encoder for 800G Optical Communication System.
ICTA
Qingyi Xie, Ziyuan Luo, Shanlin Xiao, Kai Wang, Zhiyi Yu
2021 J jnl
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning.
Neurocomputing
Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao, Zhiyi Yu
2021 J jnl
OERFF: A Vehicle Re-Identification Method Based on Orientation Estimation and Regional Feature Fusion.
IEEE Access
Bin Zheng, Zhengbao Lei, Chen Tang, Jin Wang, Zhuofan Liao, Zhiyi Yu, Yiming Xie
2020 C conf
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection.
ISCAS
Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu
2020 — conf
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs.
ICTA
Weikun Liu, Junshu Lin, Xusheng Li, Shanlin Xiao, Zhiyi Yu
2020 — conf
An Asynchronous Convolution Process Engine forVGG-16 Neural Network.
ICTA
Junshu Lin, Weikun Liu, Xusheng Li, Shanlin Xiao, Zhiyi Yu
2020 J jnl
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network.
CoRR
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2020 J jnl
DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.
IEICE Electron. Express
Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie
2020 J jnl
Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing.
IEEE Trans. Biomed. Circuits Syst.
Shanlin Xiao, Wei Liu, Yuhao Guo, Zhiyi Yu
2020 J jnl
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu
2020 B conf
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs.
ICPR
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
2020 J jnl
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs.
CoRR
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
2020 B conf
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks.
IJCNN
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2020 J jnl
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks.
CoRR
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2019 J jnl
A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People.
IEEE Trans. Circuits Syst. Video Technol.
Xiaobai Chen, Jinglong Xu, Zhiyi Yu
2018 J jnl
A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaobai Chen, Zhiyi Yu
2018 — conf
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration.
APSIPA
Xiaobai Chen, Shanlin Xiao, Zhiyi Yu
2018 C conf
An Automatic Task Partition Method for Multi-core System.
ISCAS
Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu
2017 J jnl
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sai Manoj P. D., Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu
2017 — conf
A fast and energy efficient FPGA-based system for real-time object tracking.
APSIPA
Xiaobai Chen, Jinlong Xu, Zhiyi Yu
2017 J jnl
A multi-core-based heterogeneous parallel turbo decoder.
IEICE Electron. Express
Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
2017 J jnl
An FPGA-Based Hardware Accelerator for Traffic Sign Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Weijing Shi, Xin Li, Zhiyi Yu, Gary Overett
2017 — conf
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.
ASICON
Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2017 — conf
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory.
ASICON
Baofa Huang, Ningyuan Yin, Zhiyi Yu
2015 J jnl
A 65 nm Cryptographic Processor for High Speed Pairing Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng
2015 J jnl
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng
2015 — conf
A configurable SoC design for information security.
ASICON
Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng
2015 — conf
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.
ASICON
Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng
2015 — conf
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer.
CICC
Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P. D., Hao Yu
2015 J jnl
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
2015 J jnl
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability.
IEEE Trans. Very Large Scale Integr. Syst.
Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu
2015 J jnl
Non-binary digital calibration for split-capacitor DAC in SAR ADC.
IEICE Electron. Express
Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng
2015 — conf
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.
ASICON
Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng
2015 J jnl
Special Issue on Emerging Many-Core Systems for Exascale Computing.
ACM J. Emerg. Technol. Comput. Syst.
Masoud Daneshtalab, Farhad Mehdipour, Zhiyi Yu, Hannu Tenhunen
2014 J jnl
A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
2014 — conf
Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification.
ISIC
Lijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng
2014 J jnl
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng
2014 J jnl
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2014 J jnl
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.
IEEE Trans. Circuits Syst. II Express Briefs
Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng
2013 — conf
A 2D mesh NoC with self-configurable and shared-FIFOs routers.
ASICON
Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng
2013 — conf
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.
ISSCC
Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu
2013 — conf
A fast multi-core virtual platform and its application on software development.
ASICON
Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng
2013 — conf
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks.
ASICON
Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng
2013 C conf
A low power register file with asynchronously controlled read-isolation and software-directed write-discarding.
ISCAS
Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu
2013 — conf
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform.
ASICON
Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng
2013 J jnl
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang
2013 — conf
Efficient distributed memory management in a multi-core H.264 decoder on FPGA.
ISSoC
Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch
2013 — conf
Efficient implementation of 3780-point FFT on a 16-core processor.
ASICON
Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng
2013 — conf
H.264 video parallel decoder on a 24-core processor.
ASICON
Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng
2013 C conf
Implementation and optimization of 3780-point FFT on multi-core system.
ISCAS
Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Jiayi Sheng, Haofan Yang
2013 J jnl
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.
IEEE Trans. Very Large Scale Integr. Syst.
Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng
2013 C conf
Time-Division-Multiplexer based routing algorithm for NoC system.
ISCAS
Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Liyang Zhou
2012 J jnl
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2012 J jnl
A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform.
IEICE Trans. Inf. Syst.
Bei Huang, Kaidi You, Yun Chen, Zhiyi Yu, Xiaoyang Zeng
2012 — conf
A low-cost architecture for multi-mode Reed-Solomon decoder.
ISOCC
Yun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng
2012 C conf
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.
ISCAS
Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng
2012 — conf
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms.
ISSCC
Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng
2012 J jnl
Design of a high information-density multiple valued 2-read 1-write register file.
IEICE Electron. Express
Yuejun Zhang, Pengjun Wang, Baoyu Xiong, Zhiyi Yu
2012 J jnl
Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform.
IEICE Trans. Commun.
Wenhua Fan, Chen Chen, Yun Chen, Zhiyi Yu, Xiaoyang Zeng
2012 C conf
Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability.
ISCAS
Yueming Yang, Zewen Shi, Jianming Yu, Liulin Zhong, Xiaoyang Zeng, Zhiyi Yu
2012 C conf
Task-binding based branch-and-bound algorithm for NoC mapping.
ISCAS
Liyang Zhou, Ming-e Jing, Liulin Zhong, Zhiyi Yu, Xiaoyang Zeng
2011 J jnl
A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs.
IEICE Trans. Inf. Syst.
Zewen Shi, Xiaoyang Zeng, Zhiyi Yu
2011 — conf
A channel estimator for LTE downlink mapped on a multi-core processor platform.
ASICON
Maofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng
2011 — conf
A control scheme for a 65nm 32×32b 4-read 2-write register file.
ASICON
Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng
2011 — conf
A low power 1.0 GHz VCO in 65nm-CMOS LP-process.
ASICON
Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2011 — conf
A method of quadratic programming for mapping on NoC architecture.
ASICON
Jiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng
2011 C conf
A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip.
ISCAS
Zewen Shi, Yueming Yang, Xiaoyang Zeng, Zhiyi Yu
2011 — conf
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.
ASICON
Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou
2011 — conf
Design of a single-ended cell based 65nm 32×32b 4R2W register file.
ASICON
Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2011 C conf
Fault tolerant computing for stream DSP applications using GALS multi-core processors.
ISCAS
Zhiyi Yu, Zewen Shi, Xiaoyang Zeng
2011 — conf
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs.
ASICON
Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu
2010 J jnl
A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yan Ying, Dan Bao, Zhiyi Yu, Xiaoyang Zeng, Yun Chen
2010 J jnl
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Zhiyi Yu, Bevan M. Baas
2010 C conf
A scalable and fault-tolerant routing algorithm for NoCs.
ISCAS
Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu
2009 J jnl
A 167-Processor Computational Platform in 65 nm CMOS.
IEEE J. Solid State Circuits
Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas
2009 J jnl
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Zhiyi Yu, Bevan M. Baas
2008 C conf
A low-area interconnect architecture for chip multiprocessors.
ISCAS
Zhiyi Yu, Bevan M. Baas
2008 J jnl
Architecture and Evaluation of an Asynchronous Array of Simple Processors.
J. Signal Process. Syst.
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas
2008 J jnl
AsAP: An Asynchronous Array of Simple Processors.
IEEE J. Solid State Circuits
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas
2007 J jnl
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. Very Large Scale Integr. Syst.
Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
2007 J jnl
A Shared Memory Module for Asynchronous Arrays of Processors.
EURASIP J. Embed. Syst.
Michael J. Meeuwsen, Zhiyi Yu, Bevan M. Baas
2007 J jnl
AsAP: A Fine-Grained Many-Core Platform for DSP Applications.
IEEE Micro
Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung
2006 — conf
An asynchronous array of simple processors for dsp applications.
ISSCC
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas
2006 — conf
Hardware and applications of AsAP: An asynchronous array of simple processors.
Hot Chips Symposium
Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin
2006 C conf
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
ICCD
Zhiyi Yu, Bevan M. Baas
2006 — conf
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.
ISVLSI
Zhiyi Yu, Bevan M. Baas
1998 J jnl
Optical measurement system for characterizing compound semiconductor interface and surface states.
IEEE Trans. Instrum. Meas.
Matthias Passlack, Ronald N. Legge, Diana Convey, Zhiyi Yu, Jonathan K. Abrokwah