Zhiyao Xie - RankMe

106 papers A* 15A 15B 2Journal 55Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A New Benchmark for the Appropriate Evaluation of RTL Code Optimization. CoRR Yao Lu, Shang Liu, Hangan Zhou, Wenji Fang, Qijun Zhang, Zhiyao Xie
2026	J	`jnl`	A noise-assistant network for tampering detection via inconspicuous feature enhancement and multi-perspective perception. Expert Syst. Appl. Zhiyao Xie, Xiaochen Yuan, Chan-Tong Lam, Guoheng Huang, Nuno Lourenço
2026	—	`conf`	PF-LLM: Large Language Model Hinted Hardware Prefetching. ASPLOS (2) Ceyu Xu, Xiangfeng Sun, Weihang Li, Chen Bai, Bangyan Wang, Mengming Li, Zhiyao Xie, Yuan Xie
2026	—	`conf`	ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. ASP-DAC Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025	—	`conf`	A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA. CoRR Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
2025	J	`jnl`	A Two-Phase Scheme by Integration of Deep and Corner Feature for Balanced Copy-Move Forgery Localization. IEEE Trans. Ind. Informatics Tong Liu, Xiaochen Yuan, Zhiyao Xie, Kaiqi Zhao, Guoheng Huang, Chi-Man Pun
2025	A*	`conf`	ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. DAC Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025	J	`jnl`	ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. CoRR Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025	J	`jnl`	An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qijun Zhang, Mengming Li, Andrea Mondelli, Zhiyao Xie
2025	J	`jnl`	ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design. CoRR Qijun Zhang, Yao Lu, Mengming Li, Shang Liu, Zhiyao Xie
2025	—	`conf`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2025	A*	`conf`	AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling. DAC Qijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie
2025	J	`jnl`	AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling. CoRR Qijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie
2025	A*	`conf`	CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. ICLR Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie
2025	J	`jnl`	CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. CoRR Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie
2025	J	`jnl`	DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning. CoRR Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang
2025	A*	`conf`	ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. DAC Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan
2025	J	`jnl`	ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. CoRR Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan
2025	—	`conf`	FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. ASP-DAC Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie
2025	A	`conf`	GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. ICCAD Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie
2025	J	`jnl`	GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model. CoRR Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie
2025	A	`conf`	HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. ICCAD Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie
2025	J	`jnl`	HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. CoRR Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie
2025	J	`jnl`	Image Manipulation Localization Using Dual-Shallow Feature Pyramid Fusion and Boundary Contextual Incoherence Enhancement. IEEE Trans. Emerg. Top. Comput. Intell. Yan Xiang, Xiaochen Yuan, Kaiqi Zhao, Tong Liu, Zhiyao Xie, Guoheng Huang, Jianqing Li
2025	A*	`conf`	Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency. HPCA Mengming Li, Qijun Zhang, Yongqing Ren, Zhiyao Xie
2025	J	`jnl`	Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency. CoRR Mengming Li, Qijun Zhang, Yongqing Ren, Zhiyao Xie
2025	J	`jnl`	LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization. ACM Trans. Design Autom. Electr. Syst. Cong Jiang, Haoyang Sun, Dan Feng, Zhiyao Xie, Benjamin Tan, Kang Liu
2025	A*	`conf`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. CoRR Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. CoRR Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2025	—	`conf`	PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. ASP-DAC Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen
2025	—	`conf`	Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. ASP-DAC Qijun Zhang, Zhiyao Xie
2025	A*	`conf`	Profile-Guided Temporal Prefetching. ISCA Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie
2025	J	`jnl`	Profile-Guided Temporal Prefetching. CoRR Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie
2025	J	`jnl`	RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. CoRR Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025	—	`conf`	SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. ASP-DAC Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma
2025	A*	`conf`	SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models. EMNLP Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie
2025	A*	`conf`	SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. DAC Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025	J	`jnl`	SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. CoRR Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025	—	`conf`	Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. ASP-DAC Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie
2025	J	`jnl`	Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2024	B	`conf`	APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level. ASPDAC Tao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie
2024	A*	`conf`	Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. DAC Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang
2024	J	`jnl`	Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. CoRR Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang
2024	A*	`conf`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2024	J	`jnl`	AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling. Expert Syst. Appl. Kaiqi Zhao, Xiaochen Yuan, Tong Liu, Yan Xiang, Zhiyao Xie, Guoheng Huang, Li Feng
2024	J	`jnl`	Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Peng, Tingyuan Liang, Jingbo Jiang, Yipu Zhang, Zhe Lin, Zhiyao Xie, Wei Zhang
2024	A	`conf`	EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. ICCAD Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen, Hai Helen Li
2024	J	`jnl`	Erratum to: Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	J	`jnl`	FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang
2024	J	`jnl`	FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. CoRR Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie
2024	J	`jnl`	Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	A	`conf`	OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. ICCAD Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2024	J	`jnl`	Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. CoRR Qijun Zhang, Zhiyao Xie
2024	B	`conf`	RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. ASPDAC Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie
2024	J	`jnl`	ShortCircuit: AlphaZero-Driven Circuit Design. CoRR Dimitrios Tsaras, Antoine Grosnit, Lei Chen, Zhiyao Xie, Haitham Bou-Ammar, Mingxuan Yuan
2024	J	`jnl`	SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. CoRR Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie
2024	J	`jnl`	The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	J	`jnl`	Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Tunhou Zhang, Jiang Hu, Yiran Chen
2024	A	`conf`	Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies. ISLPED Yao Lu, Qijun Zhang, Zhiyao Xie
2023	—	`conf`	A Noise Convolution Network for Tampering Detection. ICANN (10) Zhiyao Xie, Xiaochen Yuan, Chan-Tong Lam, Guoheng Huang
2023	—	`conf`	Deep Subspace K-Means Clustering for Syringe Defect Detection Without Defective Samples. DSIE Fei Yan, Xiaodong Wang, Longfu Hong, Zhiyao Xie
2023	J	`jnl`	EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. CoRR Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen
2023	—	`conf`	Efficient Runtime Power Modeling with On-Chip Power Meters. ISPD Zhiyao Xie
2023	A	`conf`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2023	—	`conf`	Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. ASP-DAC Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen
2023	A	`conf`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	J	`jnl`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	A	`conf`	PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. ICCAD Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie
2023	J	`jnl`	PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. CoRR Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie
2023	A*	`conf`	PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. DAC Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang
2023	A*	`conf`	PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. DAC Afzal Ahmad, Zhiyao Xie, Wei Zhang
2023	—	`conf`	RA-Net: A Deep Learning Approach Based on Residual Structure and Attention Mechanism for Image Copy-Move Forgery Detection. ICANN (10) Kaiqi Zhao, Xiaochen Yuan, Zhiyao Xie, Guoheng Huang, Li Feng
2023	J	`jnl`	RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2023	J	`jnl`	RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. CoRR Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie
2023	—	`conf`	Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. ASP-DAC Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen
2023	J	`jnl`	SPA-Net: A Deep Learning Approach Enhanced Using a Span-Partial Structure and Attention Mechanism for Image Copy-Move Forgery Detection. Sensors Kaiqi Zhao, Xiaochen Yuan, Zhiyao Xie, Yan Xiang, Guoheng Huang, Li Feng
2023	—	`conf`	Security and Reliability Challenges in Machine Learning for EDA: Latest Advances. ISQED Zhiyao Xie, Tao Zhang, Yifeng Peng
2023	J	`jnl`	The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Jiang Hu, Yiran Chen
2022	A	`conf`	DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. ICCAD Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu
2022	J	`jnl`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2022	J	`jnl`	Intelligent Circuit Design and Implementation with Machine Learning. CoRR Zhiyao Xie
2022	J	`jnl`	Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Chen-Chia Chang, Jingyu Pan, Yiran Chen
2022	A	`conf`	Robustify ML-Based Lithography Hotspot Detectors. ICCAD Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen
2022	J	`jnl`	The Dark Side: Security Concerns in Machine Learning for EDA. CoRR Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Yiran Chen
2022	J	`jnl`	Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data. CoRR Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen
2022	A*	`conf`	Towards collaborative intelligence: routability estimation based on decentralized private data. DAC Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen
2021	A*	`conf`	APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das
2021	A	`conf`	Automatic Routability Predictor Development Using Neural Architecture Search. ICCAD Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen
2021	—	`conf`	Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. ASP-DAC Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen
2020	J	`jnl`	Automatic Routability Predictor Development Using Neural Architecture Search. CoRR Jingyu Pan, Chen-Chia Chang, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen
2020	—	`conf`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	J	`jnl`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	A	`conf`	Fast IR Drop Estimation with Machine Learning : Invited Paper. ICCAD Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen
2020	J	`jnl`	Fast IR Drop Estimation with Machine Learning. CoRR Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen
2020	J	`jnl`	Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. CoRR Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen
2020	—	`conf`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. ASP-DAC Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	J	`jnl`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. CoRR Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	A	`conf`	Routing-Free Crosstalk Prediction. ICCAD Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam
2019	A	`conf`	Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
2018	A	`conf`	RouteNet: routability prediction for mixed-size designs using convolutional neural network. ICCAD Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu